Empirical computation of reject ratio in VLSI testing

Abstract

Among significant components of testing cost are test-length, reject ratio, and lost-yield. In this paper a new approach is proposed to estimate the reject ratio. The empirical model is based on test-data properties that are believed to be invariant for a wide range of manufacturing technologies and types of tests. The analysis is carried out entirely in terms of the device test data, as might be available from a wafer probe. Experimental results demonstrate the robustness of the model.