Heuristic technology mapper for LUT based FPGAs

Abstract

One of the main objective in the process of mapping a circuit onto a look-Up Table (LUT) based FPGA is to minimize the number of LUTs required to implement the circuit. A new top-down technology mapper algorithm is discussed in this paper which aims at minimizing number of LUTs needed for mapping the digital circuit. The algorithm makes use of combination of node selection and covering heuristics using which maximum number of DAG nodes are covered by a selected LUT. The results obtained are better than Chortle, Level-map and Flow-map-r technology mapper algorithms.