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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)最新文献

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On the design of self-checking functional units based on Shannon circuits 基于香农电路的自检功能单元设计
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307524
M. Favalli, C. Metra
{"title":"On the design of self-checking functional units based on Shannon circuits","authors":"M. Favalli, C. Metra","doi":"10.1145/307418.307524","DOIUrl":"https://doi.org/10.1145/307418.307524","url":null,"abstract":"This paper investigates the application of Shannon (BDD) circuits, that feature interesting low-power capabilities, to the design of self-checking functional units. A technique is proposed that, by using a time redundancy approach, makes this kind of circuits totally self-checking with respect to stuck-at-faults. For a set of possibly used pass-transistor-based CMOS implementations, we show that the totally self-checking or the strongly fault secure properties hold for a wider set of realistic faults, including transistors stuck-open/on and bridgings.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115022180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Approximate equivalence verification of sequential circuits via genetic algorithms 基于遗传算法的顺序电路近似等效验证
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307431
Fulvio Corno, M. Reorda, Giovanni Squillero
{"title":"Approximate equivalence verification of sequential circuits via genetic algorithms","authors":"Fulvio Corno, M. Reorda, Giovanni Squillero","doi":"10.1145/307418.307431","DOIUrl":"https://doi.org/10.1145/307418.307431","url":null,"abstract":"We have presented VEGA2: a Genetic Algorithm-based approach to the problem of equivalence verification of sequential circuits. Although sacrificing the exactness of the verification, the advantages of such an approach lie in the ability to handle large designs and in the possibility to easily trade off CPU time with confidence on the result (by tuning the maximum number of generations). VEGA2 is not a replacement for exact verification tools, but a complement: when the complexity of the circuits prevents the use of a BDD-based algorithm, it is still able to provide meaningful results. We also presented a prototypical tool and experimental analysis that shows that VEGA2 is able to provide a larger number of correct results than both an exact method and the previous GA-based approach. Thus it is able increase confidence on the validity of an optimization process.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114175883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hardware synthesis from C/C++ 硬件合成从C/ c++
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307529
Abhijit Ghosh, J. Kunkel, S. Liao
{"title":"Hardware synthesis from C/C++","authors":"Abhijit Ghosh, J. Kunkel, S. Liao","doi":"10.1145/307418.307529","DOIUrl":"https://doi.org/10.1145/307418.307529","url":null,"abstract":"Before attempting to synthesize hardware from a programming language like C or C++, we need to introduce additional semantics to be able to describe hardware behavior accurately. In particular, concurrency, reactivity, communication mechanisms, and event handling semantics need to be added, Also, a synthesizable subset of the language needs to be defined, together with synthesis semantics for programming language constructs. With these enhancements, it is possible to create C/C++ descriptions of hardware at the well-understood RTL and behavioral levels of abstraction, providing an opportunity to leverage existing, mature hardware-synthesis technology that has been developed in the context of HDL based synthesis to create a C/C++ synthesis system. In this paper, we will present some of the key ingredients of a C/C++ synthesis system and elaborate on the challenges of hardware synthesis from C/C++.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115262578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Multi-language system design 多语言系统设计
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307591
A. Jerraya, R. Ernst
{"title":"Multi-language system design","authors":"A. Jerraya, R. Ernst","doi":"10.1145/307418.307591","DOIUrl":"https://doi.org/10.1145/307418.307591","url":null,"abstract":"The design of large systems, like a mobile telecommunication terminal or the electronic parts of an airplane or a car, may require the participation of several groups belonging to different companies and using different design methods, languages and tools. The concept of multi-language specification aims at coordinating different cultures through the unification of the languages, formalism and notations. This hot topic discusses the main issues and approaches to multi-language design. Two research directions are currently being explored by the EDA community. The first is based on the computation models underlying the languages while the second deals with the specification languages themselves.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121778108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Efficient techniques for accurate extraction and modeling of substrate coupling in mixed-signal IC's 混合信号集成电路中衬底耦合精确提取和建模的有效技术
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307531
J. P. Costa, L. M. Silveira, M. Chou
{"title":"Efficient techniques for accurate extraction and modeling of substrate coupling in mixed-signal IC's","authors":"J. P. Costa, L. M. Silveira, M. Chou","doi":"10.1145/307418.307531","DOIUrl":"https://doi.org/10.1145/307418.307531","url":null,"abstract":"Accurate modeling of noise coupling effects due to crosstalk via the substrate is an increasingly important concern for the design and verification of mixed analog-digital systems. In this paper we present a technique to accelerate the model computation using BEM methods that can be used for accurate and efficient extraction of substrate coupling parameters in mixed-signal designs.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123822868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Combinational equivalence checking using satisfiability and recursive learning 利用可满足性和递归学习的组合等价检验
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307477
Joao Marques-Silva, T. Glaß
{"title":"Combinational equivalence checking using satisfiability and recursive learning","authors":"Joao Marques-Silva, T. Glaß","doi":"10.1145/307418.307477","DOIUrl":"https://doi.org/10.1145/307418.307477","url":null,"abstract":"The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. Previously, several approaches have been proposed for solving this problem. Still, the hardness of the problem and the ever-growing complexity of logic circuits motivates studying and developing alternative solutions. In this paper we study the application of Boolean satisfiability (SAT) algorithms for solving the combinational equivalence checking (CEC) problem. Although existing SAT algorithms are in general ineffective for solving CEC, in this paper we show how to improve SAT algorithms by extending and applying recursive learning techniques to the analysis of instances of SAT. This in turn provides a new alternative and competitive approach for solving CEC. Preliminary experimental results indicate that the proposed improved SAT algorithm can be useful for a large variety of instances of CEC, in particular when compared with pure BDD-based approaches.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"21 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126188767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 105
A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine 用抽象状态机实现Verilog-VHDL仿真互操作性的形式化语义
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307520
H. Sasaki
{"title":"A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine","authors":"H. Sasaki","doi":"10.1145/307418.307520","DOIUrl":"https://doi.org/10.1145/307418.307520","url":null,"abstract":"A formal semantic analysis for Verilog-HDL and VHDL is provided in order to give the simulation model especially focusing on signal scheduling and timing control mechanism. Our semantics is faithful to LRM and is expected to become a coherent first step for a future semantic interoperability analysis on multisemantic-domain such as Verilog-ARMS and VHDL-AMS. By ignoring the differences of the two simulation cycles, we can use the common semantic functions and the common simulation cycle.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129902811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A CAD framework for generating self-checking multipliers based on residue codes 基于剩余码的自检乘法器的CAD生成框架
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307471
I. Alzaher-Noufal, M. Nicolaidis
{"title":"A CAD framework for generating self-checking multipliers based on residue codes","authors":"I. Alzaher-Noufal, M. Nicolaidis","doi":"10.1145/307418.307471","DOIUrl":"https://doi.org/10.1145/307418.307471","url":null,"abstract":"The basic drawbacks related to the design of self-checking circuits include high hardware cost and design effort. Recent developments on self-checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware cost in self-checking data paths for the majority of basic data path blocks such as, adders, ALUs, shifters, register files, etc. However, parity prediction self-checking multipliers involve hardware overhead significantly higher than for other blocks. Thus, large multipliers will increase significantly the hardware overhead of the whole data path. Residue arithmetic codes allow to reduce this cost The tools presented in this paper generate automatically self-checking multipliers using such codes. They complete our tools using parity prediction for various other blocks, and enable automatic generation of low cost self-checking data paths.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122150774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Self recovering controller and datapath codesign 自恢复控制器与数据通路协同设计
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307571
S. Hamilton, A. Orailoglu, Andre Hertwig
{"title":"Self recovering controller and datapath codesign","authors":"S. Hamilton, A. Orailoglu, Andre Hertwig","doi":"10.1145/307418.307571","DOIUrl":"https://doi.org/10.1145/307418.307571","url":null,"abstract":"As society has become more reliant on electronics, the need for fault tolerant ICs has increased. This has resulted in significant research into both fault tolerant controller design, and mechanisms for datapath fault tolerance insertion. By treating these two issues separately, previous work has failed to address compatibility issues, as well as efficient codesign methodologies. In this paper, we present a unified approach to detecting control and datapath faults through the datapath, along with a method for fault identification and reconfiguration. By detecting control faults in the datapath, we avoid the area and performance overhead of detecting control faults through duplication or error checking codes. The result is a complete design methodology for self recovering architectures capable of far more efficient solutions than previous approaches.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116181435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automating the sizing of analog CMOS circuits by consideration of structural constraints 考虑结构约束的模拟CMOS电路尺寸自动化
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) Pub Date : 1999-01-01 DOI: 10.1145/307418.307516
R. Schwencker, J. Eckmueller, H. Graeb, K. Antreich
{"title":"Automating the sizing of analog CMOS circuits by consideration of structural constraints","authors":"R. Schwencker, J. Eckmueller, H. Graeb, K. Antreich","doi":"10.1145/307418.307516","DOIUrl":"https://doi.org/10.1145/307418.307516","url":null,"abstract":"In this paper a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and are introduced as structural constraints into the sizing process. Systematic consideration of these structural constraints during the automatic sizing prevents pathologically sized circuits and speeds up the automatic sizing. The sizing is done with a sensitivity-based, iterative trust region method.","PeriodicalId":442382,"journal":{"name":"Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125281771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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