IT-Information Technology最新文献_第2页

IoPT integration on the factory floor: a case study 工厂车间的IoPT集成:案例研究

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IT-Information Technology Pub Date : 2023-06-01 DOI: 10.1515/itit-2023-0005

Alexander Raschendorfer, Thomas Frühwirth

引用次数: 0

An IoT architecture to integrate different machine tools into a compound OPC UA interface 将不同机床集成到复合OPC UA接口中的物联网架构

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IT-Information Technology Pub Date : 2023-06-01 DOI: 10.1515/itit-2023-0007

Diana Strutzenberger, M. Kunz, Lisa Magdalena Schuster, Juergen Mangler, Ronald Hinterbichler

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A framework for AI-based self-adaptive cyber-physical process systems 基于人工智能的自适应信息物理过程系统框架

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IT-Information Technology Pub Date : 2023-06-01 DOI: 10.1515/itit-2023-0001

Achim Guldner, Maximilian Hoffmann, Christian Lohr, Rüdiger Machhamer, Lukas Malburg, Marlies Morgen, Stephanie C. Rodermund, Florian Schäfer, Lars Schaupeter, Jens Schneider, Felix Theusch, R. Bergmann, Guido Dartmann, Norbert Kuhn, Stefan Naumann, I. Timm, M. Vette-Steinkamp, B. Weyers

{"title":"A framework for AI-based self-adaptive cyber-physical process systems","authors":"Achim Guldner, Maximilian Hoffmann, Christian Lohr, Rüdiger Machhamer, Lukas Malburg, Marlies Morgen, Stephanie C. Rodermund, Florian Schäfer, Lars Schaupeter, Jens Schneider, Felix Theusch, R. Bergmann, Guido Dartmann, Norbert Kuhn, Stefan Naumann, I. Timm, M. Vette-Steinkamp, B. Weyers","doi":"10.1515/itit-2023-0001","DOIUrl":"https://doi.org/10.1515/itit-2023-0001","url":null,"abstract":"Abstract Digital transformation is both an opportunity and a challenge. To take advantage of this opportunity for humans and the environment, the transformation process must be understood as a design process that affects almost all areas of life. In this paper, we investigate AI-Based Self-Adaptive Cyber-Physical Process Systems (AI-CPPS) as an extension of the traditional CPS view. As contribution, we present a framework that addresses challenges that arise from recent literature. The aim of the AI-CPPS framework is to enable an adaptive integration of IoT environments with higher-level process-oriented systems. In addition, the framework integrates humans as actors into the system, which is often neglected by recent related approaches. The framework consists of three layers, i.e., processes, semantic modeling, and systems and actors, and we describe for each layer challenges and solution outlines for application. We also address the requirement to enable the integration of new networked devices under the premise of a targeted process that is optimally designed for humans, while profitably integrating AI and IoT. It is expected that AI-CPPS can contribute significantly to increasing sustainability and quality of life and offer solutions to pressing problems such as environmental protection, mobility, or demographic change. Thus, it is all the more important that the systems themselves do not become a driver of resource consumption.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":"65 1","pages":"113 - 128"},"PeriodicalIF":0.9,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43928188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

IoPT: internet of processes and things IoPT:过程和物联网

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IT-Information Technology Pub Date : 2023-06-01 DOI: 10.1515/itit-2023-0054

Christoph Pollak

引用次数: 0

Frontmatter 头版头条

IT-Information Technology Pub Date : 2023-06-01 DOI: 10.1515/itit-2023-frontmatter3

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Optimizing multi-level ReRAM memory for low latency and low energy consumption 优化多级ReRAM内存以实现低延迟和低能耗

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IT-Information Technology Pub Date : 2023-05-01 DOI: 10.1515/itit-2023-0022

Shima Hosseinzadeh, Marius Klemm, Georg Fischer, D. Fey

{"title":"Optimizing multi-level ReRAM memory for low latency and low energy consumption","authors":"Shima Hosseinzadeh, Marius Klemm, Georg Fischer, D. Fey","doi":"10.1515/itit-2023-0022","DOIUrl":"https://doi.org/10.1515/itit-2023-0022","url":null,"abstract":"Abstract With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":"65 1","pages":"52 - 64"},"PeriodicalIF":0.9,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46377268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Timing-accurate simulation framework for NVM-based compute-in-memory architecture exploration 基于虚拟机的内存计算架构探索的定时精确仿真框架

IF 0.9

IT-Information Technology Pub Date : 2023-05-01 DOI: 10.1515/itit-2023-0019

Vincent Rietz, Christopher Münch, M. Mayahinia, M. Tahoori

{"title":"Timing-accurate simulation framework for NVM-based compute-in-memory architecture exploration","authors":"Vincent Rietz, Christopher Münch, M. Mayahinia, M. Tahoori","doi":"10.1515/itit-2023-0019","DOIUrl":"https://doi.org/10.1515/itit-2023-0019","url":null,"abstract":"Abstract Data-intensive applications have a huge demand on processor-memory communication. To reduce the amount of data transfers and their associated latency and energy, Compute-in-Memory (CIM) architectures can be used to perform operations ranging from simple binary operations to more complex operations such as additions and matrix-vector multiplications directly within the memory. However, proper adjustments to the memory hierarchy are needed to enable the execution of CIM operations. To evaluate the trade-off between the usage of different emerging non-volatile memories for CIM and conventional computing architectures, this work extends the widely used gem5 simulation framework with an extensible timing-aware main memory CIM simulation capability. This framework is used to analyze the performance of CIM extended main memory with various emerging memory technologies, namely Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), Redox-based RAM (ReRAM) and Phase-Change Memory (PCM). We evaluate different workloads from the PolyBench/C benchmark suite and other selected examples. In comparison to a processor-centric system, the results show a significant reduction in execution time for the majority of applications.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":"65 1","pages":"13 - 29"},"PeriodicalIF":0.9,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45209748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of sneak paths on in-memory logic design in memristive crossbars 偷偷路径对记忆交叉杆内存逻辑设计的影响

IF 0.9

IT-Information Technology Pub Date : 2023-05-01 DOI: 10.1515/itit-2023-0020

K. Datta, Arighna Deb, Abhoy Kole, R. Drechsler

{"title":"Impact of sneak paths on in-memory logic design in memristive crossbars","authors":"K. Datta, Arighna Deb, Abhoy Kole, R. Drechsler","doi":"10.1515/itit-2023-0020","DOIUrl":"https://doi.org/10.1515/itit-2023-0020","url":null,"abstract":"Abstract Resistive Random Access Memory (RRAM), also termed as memristors, is a non-volatile memory where information is stored in memory cells in the form of resistance. Due to its non-volatile resistive switching properties, memristors, in the form of crossbars, are used for storing information, neuromorpic computing, and logic synthesis. In spite of the wide range of applications, memristive crossbars suffer from a so-called sneak path problem which results in an erroneous reading of memristor’s state. Till date, no or very few logic synthesis approaches for in-memory computing have considered the sneak path problem during the realizations of Boolean functions. In other words, the effects of sneak paths on the Boolean function realizations in crossbars still remain an open problem. In this paper, we have addressed this issue. In particular, we study the impacts of function realizations in two memristive crossbar structures: Zero-Transistor-One-Resistor (0T1R) and One-Transistor-One-Resistor (1T1R) in the presence of sneak paths. Experimental analysis on IWLS and ISCAS-85 benchmarks shows that even in the presence of sneak paths, the 1T1R crossbar structures with multiple rows and columns are the most efficient as compared to the 1T1R structures with single row and multiple columns in terms of crossbar size and number of execution cycles.","PeriodicalId":43953,"journal":{"name":"IT-Information Technology","volume":"65 1","pages":"29 - 39"},"PeriodicalIF":0.9,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49226140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An RRAM-based building block for reprogrammable non-uniform sampling ADCs 用于可编程非均匀采样ADC的基于RRAM的构建块

IF 0.9

IT-Information Technology Pub Date : 2023-05-01 DOI: 10.1515/itit-2023-0021

Abhinav Vishwakarma, Markus Fritscher, Amelie Hagelauer, M. Reichenbach

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Frontmatter 头版头条

IT-Information Technology Pub Date : 2023-05-01 DOI: 10.1515/itit-2023-frontmatter1-2

引用次数: 0