优化多级ReRAM内存以实现低延迟和低能耗

IF 1 Q4 COMPUTER SCIENCE, INFORMATION SYSTEMS
Shima Hosseinzadeh, Marius Klemm, Georg Fischer, D. Fey
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引用次数: 0

摘要

摘要随着芯片尺寸的减小和在单个单元中存储多个位的能力,电阻式随机存取存储器(ReRAM)可以用来提高存储密度,使其成为下一代存储器的一种有前途的技术。然而,多级写入操作会受到诸如大延迟、高能耗和可靠性问题之类的损害。在本文中,我们研究了在元件和电路层面的瞬态模拟中,在1-晶体管-1-电阻器(1T1R)模型上影响“带验证算法的多级增量阶跃脉冲”(M-ISPVA)的不同机制,重点关注整个状态转换过程中的电阻控制和能量消耗。通过将M-ISPVA划分为触发期和控制期,我们发现晶体管在触发期内作为压控电阻在欧姆区工作,在控制期内作为电压控制限流器在饱和区工作。在触发周期中控制栅极电压可以将触发点移动到期望的写入电压,并且在控制周期中可以增加或减少每个脉冲的电阻步长以获得期望的电阻变化速度。此外,主要能量部分被消耗用于触发期间的复位操作和控制时段期间的设置操作。为了优化写入性能,在用目标读出电流和栅极电压定义电阻状态时必须采取额外的预防措施,重点是所有转换之间的均匀平衡延迟。直接多级写入操作显示67.5 % 延迟和62.5 % 与间接控制相比节能,但仅受到单向控制的影响,使其不可行。如果是4 k 位内存,更可靠的M-ISPVA面临几乎37 % 与基本ISPVA相比具有更高的延迟和能量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimizing multi-level ReRAM memory for low latency and low energy consumption
Abstract With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA.
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来源期刊
IT-Information Technology
IT-Information Technology COMPUTER SCIENCE, INFORMATION SYSTEMS-
CiteScore
3.80
自引率
0.00%
发文量
29
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