Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)最新文献_第8页

A folded 32-bit prefix tree adder in 0.16-/spl mu/m static CMOS 在0.16-/spl mu/m静态CMOS中的折叠32位前缀树加法器

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951662

A. Goldovsky, H. Srinivas, R. Kolagotla, R. Hengst

{"title":"A folded 32-bit prefix tree adder in 0.16-/spl mu/m static CMOS","authors":"A. Goldovsky, H. Srinivas, R. Kolagotla, R. Hengst","doi":"10.1109/MWSCAS.2000.951662","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951662","url":null,"abstract":"This paper presents a new prefix tree adder that is faster than previously published adder designs. The speed improvement is achieved by rearranging the logic for the computation of the sum bits in the final stage of the adder so as to exploit the differing delays with which the group-transmit, group-generate, and carries (at each and every bit position) are generated. Previous adder designs, either used group transmit signals or group propagate signals to build prefix tree for carry generation. They did not exploit the fact that in the last stage of the parallel prefix carry tree, this difference can allow rearranging of the logic for reduced logic depth. For designs where a uniform layout of the adder is not a big concern (e.g., in communication and signal processing custom chips), the negative effect of interconnect delays at the last stage of the adder can be reduced by employing a left-to-right routing of the most-significant group generate and group-transmit signals. This is useful for large word-length (greater or equal to 32) adders. Incorporating these improvements into the adder design has resulted in about 15% improvement in speed over previously proposed adder designs. A 32-bit radix-2 prefix tree adder implementation of the proposed scheme has a delay of 0.7 ns at 1.5 volts 100 C in the Lucent's 0.16-/spl mu/m static CMOS technology.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126063299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Implementation of a Temperature Monitoring Interface Circuit for PowerPC systems PowerPC系统温度监测接口电路的实现

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951595

H. Chiueh, J. Choma, J. Draper

引用次数: 8

Basics of floating-gate low-dropout voltage regulators 浮动门低压差稳压器的基本原理

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951396

A. Low, P. Hasler

引用次数: 9

Energy reduction from using selective precharge in two different logic arrays 在两个不同的逻辑阵列中使用选择性预充电减少能量

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951592

Shaoyi Wang, C. Zukowski

引用次数: 0

Mathematical unification of dynamic-element-matching methods for spectral shaping of hardware-mismatch errors 硬件失配误差谱整形动态元素匹配方法的数学统一

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951444

J. Coleman

引用次数: 2

A multi-level netlist partitioning approach to hierarchical layout design of analog ICs 模拟集成电路分层布局设计中的多级网表划分方法

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951601

P. B. Wu, R. Mack, R. Massara

引用次数: 0

A simple 2-transistor transresistor 一个简单的2晶体管变阻器

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951442

M.E. Schlannann, R. Geiger

引用次数: 5

A novel linear tunable MOS transconductor 一种新型线性可调谐MOS晶体管

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951683

Ko-Chi Kuo, A. Leuciuc

引用次数: 2

Timing analysis of block replacement algorithms on disk caches 磁盘缓存上块替换算法的时序分析

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951670

Ramakrishnan Rajamoni, R. Bhagavathula, Ravi Pendse

{"title":"Timing analysis of block replacement algorithms on disk caches","authors":"Ramakrishnan Rajamoni, R. Bhagavathula, Ravi Pendse","doi":"10.1109/MWSCAS.2000.951670","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951670","url":null,"abstract":"Cache memories are used to reduce the memory latency in systems. While instruction references of a CPU exhibit high temporal and spatial locality, disk references exhibit very minimal temporal and spatial locality. Owing to the fact that most of the block replacement algorithms exploit the available locality to improve cache performance, they are more effective with CPU instruction caches than with disk caches. This paper presents the results of an investigation of cache write policies and the impact of the Least Recently Used (LRU) and the Segmented LRU (SLRU) block replacement algorithms on the performance of disk caches. To obtain optimal performance at all workloads and cache sizes, an adaptive write caching policy is introduced. The adaptive write caching policy does a dynamic selection of the write policy at run time. Simulations reveal that when the cache size is less than 2 MB, caches employing adaptive write caching policy are 17% faster over caches employing write-back policy. For cache sizes of 16 MB and above the performance improvement is 9%. The performance improvement of caches employing adaptive write caching policy over caches employing write-through policy is 2.65% for cache sizes of 2 MB and is 27%, for cache sizes of 16 MB and above. The adaptive write caching policy yields optimum performance for many of the disk workloads and disk cache sizes.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116929534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm 一种采用分解欧几里得算法的Reed-Solomon解码器

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI: 10.1109/MWSCAS.2000.951634

Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, Chen-Yi Lee

引用次数: 2