模拟集成电路分层布局设计中的多级网表划分方法

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Pub Date : 2000-08-08 DOI:10.1109/MWSCAS.2000.951601

P. B. Wu, R. Mack, R. Massara

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引用次数: 0

摘要

提出了一种用于模拟版图分层设计的算法网表划分方法。除了考虑路由可达性外，分区还在模拟性能和区域效率约束下运行。多层隔板嵌入了内置移动操作符，使设计人员能够平衡质量和设计时间。算例结果表明了该方法的有效性。

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A multi-level netlist partitioning approach to hierarchical layout design of analog ICs

An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.

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Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)

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