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A 0.45V-to-2.7V inductive-coupling level shifter 一个0.45 v -2.7 v电感耦合电平移位器
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-12-01 DOI: 10.1109/ASSCC.2010.5716591
Keita Takatsu, K. Niitsu, T. Shidei, N. Miura, T. Kuroda
{"title":"A 0.45V-to-2.7V inductive-coupling level shifter","authors":"Keita Takatsu, K. Niitsu, T. Shidei, N. Miura, T. Kuroda","doi":"10.1109/ASSCC.2010.5716591","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716591","url":null,"abstract":"This paper presents a 0.45V-to-2.7V level shifter utilizing inductive coupling. Since primary and secondary coils are AC-coupled, each coil can be biased at arbitrary voltage independent from the conversion level difference. This enables both the primary and the secondary circuits to operate at the optimal operating region. In addition, the inductive coupling itself can provide an additional intermediate level-shifting by exploiting a coil-turn ratio between the primary and the secondary coils. As a result, wide-range voltage level conversion can be achieved. Test chip measurement in 65nm CMOS demonstrates voltage level conversion from 0.45V to 2.7V. Compared to a conventional level shifter, the primary voltage is reduced by 0.24V. In addition, the energy-delay product is reduced to 1/8.","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128587540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 30Gb/s/link 2.2Tb/s/mm2 inductively-coupled injection-locking CDR 30Gb/s/链路2.2Tb/s/mm2电感耦合注入锁定CDR
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-12-01 DOI: 10.1109/ASSCC.2010.5716562
Yasuhiro Take, N. Miura, T. Kuroda
{"title":"A 30Gb/s/link 2.2Tb/s/mm2 inductively-coupled injection-locking CDR","authors":"Yasuhiro Take, N. Miura, T. Kuroda","doi":"10.1109/ASSCC.2010.5716562","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716562","url":null,"abstract":"This paper presents a 30Gb/s/link 2.2Tb/s/mm2 inductive-coupling link for a high-speed DRAM interface. The data rate per layout area is the highest among DRAM interfaces reported up to now [1–11]. The proposed interface employs a high-speed injection-locking CDR technique that utilizes the derivative property of inductive coupling. Compared to conventional injection-locking CDR based on an XOR edge detector, our technique doubles the operation speed and increases the data rate to 30Gb/s/link. As a result, the data rate per layout area is increased to 2.2Tb/s/mm2, which is 2X that of the state-of-the-art inductive-coupling link [1], and 22X that of the state-of-the-art wired link [3].","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134210631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Phase-to-Digital Converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3 V 一种相位-数字转换器，用于宽调谐范围和可容PVT的ADPLL，工作电压低至0.3 V
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-12-01 DOI: 10.1109/ASSCC.2010.5716596
I. Hayashi, T. Matsubara, Satoshi Kumaki, Abul Hasan Johari, H. Ishikuro, T. Kuroda
{"title":"A Phase-to-Digital Converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3 V","authors":"I. Hayashi, T. Matsubara, Satoshi Kumaki, Abul Hasan Johari, H. Ishikuro, T. Kuroda","doi":"10.1109/ASSCC.2010.5716596","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716596","url":null,"abstract":"A Phase-to-Digital Converter (PDC), — an improved scheme of Time-to-Digital Converter (TDC) —, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":" 48","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132039998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 300- to 800-MHz de-skew clock generator for arbitrary delay 用于任意延迟的300至800兆赫的去倾斜时钟发生器
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-11-01 DOI: 10.1109/ASSCC.2010.5716597
Yu-Cheng Hung, K. Fong, Tai-Cheng Lee
{"title":"A 300- to 800-MHz de-skew clock generator for arbitrary delay","authors":"Yu-Cheng Hung, K. Fong, Tai-Cheng Lee","doi":"10.1109/ASSCC.2010.5716597","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716597","url":null,"abstract":"A low-jitter 300- to 800-MHz de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while maintaining a wide loop bandwidth. The clock skew problem is detrimental in the high speed applications, especially when the skew is longer than multi-cycles. The proposed generator was fabricated in a 0.18-μm CMOS process. The clock generator achieves a measured RMS jitter of 5.8 ps at 800 MHz with less than 100-ns settling time. The total area is 0.525 × 0.396 mm2 and the power consumption is 10.8mW from a 1.8V supply.","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125123875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A multi-mode digital controller with windowed ADC and self-calibrated DPWM for slew-enhanced switching converter 一种带加窗ADC和自校准DPWM的多模数字控制器
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-11-01 DOI: 10.1109/ASSCC.2010.5716556
Po-Hsiang Lan, Chun-Yen Tseng, Feng-Chang Yeh, Po-Chiun Huang
{"title":"A multi-mode digital controller with windowed ADC and self-calibrated DPWM for slew-enhanced switching converter","authors":"Po-Hsiang Lan, Chun-Yen Tseng, Feng-Chang Yeh, Po-Chiun Huang","doi":"10.1109/ASSCC.2010.5716556","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716556","url":null,"abstract":"Windowed ADC is an attractive solution for the high efficiency digitally-controlled converters. However its limited conversion range restricts the transient speed for the dynamic voltage scaling applications. For slew rate improvement, this work designed a multi-mode PI/PID controller incorporated with the windowed ADC operation. In addition, to make output stable with no limit cycling, a current-controlled delay-line ADC and a DPWM with self calibration loops are proposed. The prototype chip is realized in a standard 0.18-µm CMOS process. The switching frequency of the buck converter is up to 5MHz. The average current consumed in the digital controller, ADC and DPWM are 0.25, 0.2 and 0.7mA, respectively. The transient time from 1-V to 1.7-V step is 30µs that is 2.5 times faster than the conventional linear controller design.","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116827392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 10b linear interpolation DAC using body-transconductance control for AMLCD column driver 采用体-跨导控制的10b线性插值DAC用于AMLCD列驱动器
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-11-01 DOI: 10.1109/ASSCC.2010.5716581
Changbyung Park, Kiduk Kim, Sungwoo Lee, Gyu‐Sung Park, S. Ryu, G. Cho
{"title":"A 10b linear interpolation DAC using body-transconductance control for AMLCD column driver","authors":"Changbyung Park, Kiduk Kim, Sungwoo Lee, Gyu‐Sung Park, S. Ryu, G. Cho","doi":"10.1109/ASSCC.2010.5716581","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716581","url":null,"abstract":"A 10-b interpolation DAC is implemented for AMLCD column driver using 4b control of body potential via a built-in body buffer for interpolation in the buffer amplifier. Measured INL and DNL are 0.36 LSB and 0.35LSB on 10b accuracy, respectively. Each channel of driver IC has a height of 295μm, a pitch of 14μm and a static current of ΙμΑ The fabricated chip is in 90n CMOS process.","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130263805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A regulator-free 84dB DR audio-band ADC for compact digital microphones 用于紧凑型数字麦克风的无稳压器84dB DR音频带ADC
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-11-01 DOI: 10.1109/ASSCC.2010.5716631
H. Le, Sang-Gug Lee, S. Ryu
{"title":"A regulator-free 84dB DR audio-band ADC for compact digital microphones","authors":"H. Le, Sang-Gug Lee, S. Ryu","doi":"10.1109/ASSCC.2010.5716631","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716631","url":null,"abstract":"A 20kHz audio-band ADC with a single power-supply pad is implemented for a digital electret microphone. The designed low-noise preamplifier not only relaxes the ADC design requirement but also provides an excellent interface for the electret capacitor. A low power 4th-order switched-capacitor (SC) ΣΔ modulator (ΣΔΜ) converts the analog signal into lb digital. Under the single power-supply pad, the switching noise effect on the signal quality is estimated via post simulations with simplified parasitic models. Performance degradation is minimized by time-domain noise isolation (TDNI) with sufficient time-spacing between the sampling edge and the output transition. A prototype ADC was implemented in a 0.18 μm CMOS process. It operates under a minimum supply voltage of 1.6 V with total current of 420 μΑ Operating at 2.56 MHz clock frequency, it achieves 84 dB dynamic range and a 64 dB peak signal-to-(noise + distortion) ratio. The measured power supply rejection at a 100 mVpp 217 Hz square wave is −72 dB without any supply regulation.","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124340121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An ultra-low-cost RFID tag with 1.67 Gbps data rate by ink-jet printing on paper substrate 一种在纸基上喷墨打印的超低成本RFID标签，数据速率为1.67 Gbps
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-11-01 DOI: 10.1109/ASSCC.2010.5716569
Botao Shao, Qiang Chen, Y. Amin, S. M. David, Ran Liu, Li-Rong Zheng
{"title":"An ultra-low-cost RFID tag with 1.67 Gbps data rate by ink-jet printing on paper substrate","authors":"Botao Shao, Qiang Chen, Y. Amin, S. M. David, Ran Liu, Li-Rong Zheng","doi":"10.1109/ASSCC.2010.5716569","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716569","url":null,"abstract":"A fully metallic ink-jet printed passive chipless RFID tag on paper substrate is presented. The tag consists of an ultra-wide-band antenna, a microstrip transmission line with distributed shunt capacitors as information coding element which is reconfigurable by ink-jet printing process. Tapered microstrip line is employed to overcome the limitations of low conductivity and thin film thickness of ink-jet printed metal tracks. Measurement results show that the tag features a robust readability over 80 cm reading distance and a high data rate of 1.67 Gb/s.","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131247044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
A process-insensitive current-controlled delay generator with threshold voltage compensation 具有阈值电压补偿的过程不敏感的电流控制延迟发生器
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-11-01 DOI: 10.1109/ASSCC.2010.5716595
Hegong Wei, U. Chio, Sai-Weng Sin, U. Seng-Pan, R. P. Martins
{"title":"A process-insensitive current-controlled delay generator with threshold voltage compensation","authors":"Hegong Wei, U. Chio, Sai-Weng Sin, U. Seng-Pan, R. P. Martins","doi":"10.1109/ASSCC.2010.5716595","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716595","url":null,"abstract":"A process-insensitive current-controlled delay generator is presented with a large tunable range of the time delay. By adopting process variation compensation techniques in the generation of time delay, the delay generator is able to provide process-insensitive clock pulses. The circuit has been fabricated in 90nm CMOS technology, consumes 310μW from a 1. IV supply. Using, in a typical case, 20μA of reference current, it can generate a delay of 2.36 ns. The delay variation observed in 14 measured chips has shown a standard deviation of 1.24%.","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":" 29","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132188869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.3mA 240-to-500MHz 6th-order active-RC low-pass filter for ultra-wideband transceiver 用于超宽带收发器的2.3mA 240 ~ 500mhz 6阶有源rc低通滤波器
2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-11-01 DOI: 10.1109/ASSCC.2010.5716607
Le Ye, H. Liao, Congyin Shi, Junhua Liu, Ru Huang
{"title":"A 2.3mA 240-to-500MHz 6th-order active-RC low-pass filter for ultra-wideband transceiver","authors":"Le Ye, H. Liao, Congyin Shi, Junhua Liu, Ru Huang","doi":"10.1109/ASSCC.2010.5716607","DOIUrl":"https://doi.org/10.1109/ASSCC.2010.5716607","url":null,"abstract":"This paper presents a 6th-order active-RC low-pass filter with 240 MHz to 500 MHz tunable bandwidth, which is suitable for the ultra-wideband transceivers. The filter consumes only 2.3 mA from 1.8 V supply voltage, which is mainly attributed to the proposed highly power-efficient operational amplifier (Opamp) with an adaptive-biased pole-cancellation push-pull source follower as the buffer stage to drastically extend the bandwidth. The technique of high-frequency common-mode rejection using parasitic capacitor is utilized to guarantee the Opamp stability. In addition, the filter adopts the Q-tuning technique and Opamp GBW compensation mechanism, which relax the GBW requirement of the Opamp to further reduce the power consumption. The filter achieves 1.36 pW/pole/Hz normalized power, 13.1 nVA√Hz input-referred noise density, 15.9 dBm in-band IIP3, and 34 dBm out-of-band IIP3, respectively. The chip is fabricated in a standard 0.18 μm CMOS process, and occupies 0.23 mm2 silicon area without pads.","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":"426 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132656384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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