I. Hayashi, T. Matsubara, Satoshi Kumaki, Abul Hasan Johari, H. Ishikuro, T. Kuroda
{"title":"A Phase-to-Digital Converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3 V","authors":"I. Hayashi, T. Matsubara, Satoshi Kumaki, Abul Hasan Johari, H. Ishikuro, T. Kuroda","doi":"10.1109/ASSCC.2010.5716596","DOIUrl":null,"url":null,"abstract":"A Phase-to-Digital Converter (PDC), — an improved scheme of Time-to-Digital Converter (TDC) —, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).","PeriodicalId":437088,"journal":{"name":"2010 IEEE Asian Solid-State Circuits Conference","volume":" 48","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2010.5716596","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A Phase-to-Digital Converter (PDC), — an improved scheme of Time-to-Digital Converter (TDC) —, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).