一种相位-数字转换器，用于宽调谐范围和可容PVT的ADPLL，工作电压低至0.3 V

2010 IEEE Asian Solid-State Circuits Conference Pub Date : 2010-12-01 DOI:10.1109/ASSCC.2010.5716596

I. Hayashi, T. Matsubara, Satoshi Kumaki, Abul Hasan Johari, H. Ishikuro, T. Kuroda

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引用次数: 6

摘要

提出了一种相位-数字转换器(PDC)——一种时间-数字转换器(TDC)的改进方案。PDC的分辨率完全跟踪生成的时钟周期。该方案有效地减少了传统TDC的校准工作量。关键技术是数字控制耦合振荡器(DCCO)和体偏控制游标TDC。该PDC应成为宽调谐范围和耐PVT变化的全数字锁相环(ADPLL)的关键部件。

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A Phase-to-Digital Converter for wide tuning range and PVT tolerant ADPLL operating down to 0.3 V

A Phase-to-Digital Converter (PDC), — an improved scheme of Time-to-Digital Converter (TDC) —, is presented. The resolution of PDC is completely tracking to generated clock period. This scheme effectively reduces the calibration efforts in conventional TDC. The key technologies are digitally Controlled Coupled Oscillator (DCCO) and body-bias controlled vernier TDC. This PDC should be a key component of wide tuning range and PVT variation tolerant All Digital PLL (ADPLL).

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2010 IEEE Asian Solid-State Circuits Conference

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