2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping最新文献_第2页

Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip 可重构片上系统软硬件调度的动态适应

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.28

Ghaffari Fakhreddine, Benoît Miramond, F. Verdier

引用次数: 1

Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology 系统级设计方法中通信细化和硬件综合的自动化

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.17

Laurent Moss, Marc-André Cantin, G. Bois, E. Aboulhamid

{"title":"Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology","authors":"Laurent Moss, Marc-André Cantin, G. Bois, E. Aboulhamid","doi":"10.1109/RSP.2008.17","DOIUrl":"https://doi.org/10.1109/RSP.2008.17","url":null,"abstract":"Traditional register-transfer level design methodologies for systems-on-chip are failing to keep up with the growing complexity of embedded applications and architectures. A well-known solution is to raise the level of design abstraction by using system-level methodologies. The refinement from system-level specifications to concrete implementations is an essential step in a system-level design methodology. This article presents a novel methodology for the refinement from transaction-level communications to pin- and cycle-accurate protocols as well as the generation of synthesizable hardware from system-level specifications. Automatic communication refinement and hardware synthesis were successfully applied to a rover guiding system. Hand-coded and automatically generated register-transfer level modules of the rover are compared. Results show that a hardware/software implementation of the guiding system using generated register-transfer level modules has overheads of less than one percent in latency and hardware area when compared to an implementation using hand-coded modules.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130755292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Application Specific Instruction Sets and their Impact on the Design Space Requirements of a Hardware Java Virtual Machine 应用特定指令集及其对硬件Java虚拟机设计空间需求的影响

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.10

R. Wood, J. Libby, K. Kent

引用次数: 0

A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support 一种具有复杂调试支持的无线传感器网络原型方法

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.13

H. Hinkelmann, A. Reinhardt, M. Glesner

{"title":"A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support","authors":"H. Hinkelmann, A. Reinhardt, M. Glesner","doi":"10.1109/RSP.2008.13","DOIUrl":"https://doi.org/10.1109/RSP.2008.13","url":null,"abstract":"In this paper, we present a methodology for rapid prototyping of wireless sensor networks that allows to embed sophisticated debugging functionality in a mote prototype and thereby monitor entire networks. We achieve this goal by combining two fundamental concepts: the use of a re-configurable sensor node prototype platform, and an auxiliary network structure for granting a reliable communication channel for runtime debugging without interfering with the primary radio link. For the prototype platform, we propose a modular design which incorporates a single FPGA with high gate count as core of the platform. The FPGA is utilized to emulate arbitrary mote architectures and realize flexible interfaces to sensors and radio transceivers. As a major benefit, versatile debugging interfaces can additionally be implemented in the same FPGA, seamlessly integrating into the emulated mote architecture, with direct access to internal information. This easily allows to realize passive system monitors as well as active debugging control. By using a deployment support network to exchange relevant information, all motes can be monitored and controlled simultaneously by a user. The paper presents the proposed methodology, its implementation, and a practical application example in detail.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114469376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates 位流更新可重构硬件可信平台功能原型

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.24

B. Glas, Alexander Klimm, David Schwab, K. Müller-Glaser, J. Becker

引用次数: 10

A Multi-MicroBlaze Based SOC System: From SystemC Modeling to FPGA Prototyping 基于多microblaze的SOC系统:从SystemC建模到FPGA原型设计

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.15

S. Xu, H. Pollitt-Smith

引用次数: 17

Flexible Software-Hardware Network Intrusion Detection System 灵活的软硬件网络入侵检测系统

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.11

Ryan B. Proudfoot, K. Kent, E. Aubanel, Nan Chen

引用次数: 4

Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers 基于多cpu /FPGA平台的异构多处理器原型:嵌入式软件设计人员面临的新挑战

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.27

B. Senouci, Abdellah-Medjadji Kouadri-Kouadri, F. Rousseau, F. Pétrot

引用次数: 28

Using MDE for the Rapid Prototyping of Space Critical Systems MDE在空间关键系统快速成型中的应用

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.19

J. Hugues, M. Perrotin, T. Tsiodras

引用次数: 13

Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels 使用抽象级别的可配置异构MPSoC架构探索

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.18

Hao Shen, P. Gerin, F. Pétrot

{"title":"Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels","authors":"Hao Shen, P. Gerin, F. Pétrot","doi":"10.1109/RSP.2008.18","DOIUrl":"https://doi.org/10.1109/RSP.2008.18","url":null,"abstract":"Configurable processors are adopted by several latest embedded system projects to make use of application specific custom instructions for instruction level parallelism. Meanwhile, designers also use multiple processors for thread level parallelism. Configurable heterogeneous multi-processor system-on-chip (CH-MPSoC) has both parallelism advantages and seems to be a good solution for future embedded systems. Because CH-MPSoC has lots of architectural parameters, new design methodologies are required to help exploring this huge design space and finding a suitable solution for all user-defined constraints. We propose a new exploration flow using a budget based problem partitioning approach integrated with multiple abstraction levels. By using several abstraction levels, global budgets of speed, power and cost can be decomposed into detailed ones which are mapped onto each component. One special abstraction level called transaction accurate level is used in our flow to model both multi-processor architectures and configurable processors. At this level, hardware tasks and peripherals use transaction level modeling to achieve high simulation speed. Statistic information of configurable processors is abstracted and annotated to each software tasks. The execution results are used to adjust budgets and guide automatic extended instructions generation. With the Motion-JPEG case study, we illustrate detailed advantages of our CH-MPSoC exploration flow.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130190563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7