2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping最新文献

Implementation Strategies for Statistical Codec Designs in H.264/AVC Standard H.264/AVC标准中统计编解码器设计的实现策略

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.22

X. Tian, T. M. Le, Xi Jiang, Y. Lian

引用次数: 6

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding 从应用到基于asip的FPGA原型:以Turbo解码为例

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.16

O. Muller, A. Baghdadi, M. Jézéquel

引用次数: 12

Functional DIF for Rapid Prototyping 快速原型的功能DIF

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.32

W. Plishker, N. Sane, Mary Kiemb, K. Anand, S. Bhattacharyya

{"title":"Functional DIF for Rapid Prototyping","authors":"W. Plishker, N. Sane, Mary Kiemb, K. Anand, S. Bhattacharyya","doi":"10.1109/RSP.2008.32","DOIUrl":"https://doi.org/10.1109/RSP.2008.32","url":null,"abstract":"Dataflow formalisms have provided designers of digital signal processing systems with optimizations and guarantees to arrive at quality prototypes quickly. As system complexity increases, designers are expressing more types of behavior in dataflow languages to retain these implementation benefits. While the semantic range of DSP-oriented dataflow models has expanded to cover quasi-static and dynamic applications, efficient functional simulation of such applications has not. Complexity in scheduling and modeling has impeded efforts towards functional simulation that matches the final implementation. We provide this functionality by introducing a new dataflow model of computation, called enable-invoke dataflow (EIDF), that supports flexible and efficient prototyping of dataflow-based application representations. EIDF permits the natural description of actors for dynamic and static dataflow models. We integrate EIDF into the dataflow interchange format (DIF) package and demonstrate the approach on the design of a polynomial evaluation accelerator targeting an FPGA implementation. Our experiments show that a design environment based on EIDF can achieve functionally-correct simulation compared to Verilog, allowing the application designer to arrive at a verified functional simulation faster, and therefore at a functional prototype much more quickly than traditional design practices.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121831748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 121

MAJIC: A Java Application for Controlling Multiple, Heterogeneous Robotic Agents 一个用于控制多个异构机器人代理的Java应用程序

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.30

Gregory P. Ball, K. Squire, C. Martell, M. Shing

{"title":"MAJIC: A Java Application for Controlling Multiple, Heterogeneous Robotic Agents","authors":"Gregory P. Ball, K. Squire, C. Martell, M. Shing","doi":"10.1109/RSP.2008.30","DOIUrl":"https://doi.org/10.1109/RSP.2008.30","url":null,"abstract":"When teaching robotics, we have a number of constraints and desires to satisfy. We are limited by the time available to teach a class, so we need a robotic system that our students can get up to speed on quickly and easily. We are limited by robot availability, in the robots that are on hand, but also because manufacturers of inexpensive teaching robots tend to go bankrupt or change focus quickly, making it difficult to purchase new robots with the same interface as previous models. Thus, we desire an interface easily adaptable to new robots. Finally, we have recently become interested in teaching techniques for dealing with teams of possibly heterogeneous robots. All existing systems that we examined fall short in one or more of these areas, prompting our development of the The multi-agent Java interface controller (MAJIC). MAJIC was designed from the bottom up with modern software engineering principles. The interface is easy to use and learn, can be quickly adapted to new robots, and allows control of multiple robots simultaneously. This paper presents the design of this system, highlighting rapid development and clarity compared with other systems.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131523882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

RealSpec: An Executable Specification Language for Prototyping Concurrent Systems RealSpec:用于并发系统原型设计的可执行规范语言

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.9

A. Khwaja, J. E. Urban

引用次数: 4

Software for Multi Processor System on Chip: Moving an MPEG4 Decoder from Generic RISC Platforms to CELL 芯片上多处理器系统的软件:将MPEG4解码器从通用RISC平台移动到CELL

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.21

Ludovic Demontes, M. Bonaciu, P. Amblard

{"title":"Software for Multi Processor System on Chip: Moving an MPEG4 Decoder from Generic RISC Platforms to CELL","authors":"Ludovic Demontes, M. Bonaciu, P. Amblard","doi":"10.1109/RSP.2008.21","DOIUrl":"https://doi.org/10.1109/RSP.2008.21","url":null,"abstract":"This paper presents the challenges encountered during the process of moving an MPEG4 decoder implementation from Rise based platforms to CELL processor. It presents multiple implementations of MPEG4 video decoder on a CELL processor, using different software partitioning and mapping schemes. The approach starts from a generic representation of an MPEG4 video decoder, from which multiple customized MPEG4 video decoders can be obtained (i.e. different number of tasks, video resolutions, frame-rates, etc). Each of these configurations of MPEG4 video decoders was mapped and executed on a CELL processor. During previous works, this was already realized using multi-RISC based multi processor system on chip (MPSoc) platforms. However, by changing to CELL processors, new challenges and problems appeared. They must be considered and solved, in order to obtain a running MPEG4 video decoder on CELL. This paper presents these challenges and problems, along with some solutions. Finally, some performance results are presented for different MPEG4 video decoders implementations on a CELL processor. This paper is focusing on the portation only, and does not cover the final optimization phase using CELL processor specific code optimization techniques.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122850197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Integrating Abstract NoC Models within MPSoC Design 在MPSoC设计中集成抽象NoC模型

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.29

E. I. Moreno, K. Popovici, Ney Laert Vilar Calazans, A. Jerraya

引用次数: 7

Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II 利用托勒密技术确定重离子同步加速器中数字控制腔同步的带宽需求

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.26

Christopher Spies, P. Zipf, M. Glesner, H. Klingbeil

引用次数: 2

An Automated Design Flow for NoC-based MPSoCs on FPGA 基于FPGA的基于noc的mpsoc自动化设计流程

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.31

S. Lukovic, Leandro Fiorin

引用次数: 36

Co-design Architecture and Implementation for Point-Based Rendering on FPGAs fpga上基于点绘制的协同设计架构与实现

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping Pub Date : 2008-06-02 DOI: 10.1109/RSP.2008.23

Mateusz Majer, S. Wildermann, Josef Angermeier, S. Hanke, J. Teich

引用次数: 6