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Proceedings of the Twentieth International Symposium on Multiple-Valued Logic最新文献

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Step-wise synthesis of CCD MVL functions CCD MVL函数的步进合成
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122637
S. Zaky, Z. Vranesic, M. Abd-El-Barr
{"title":"Step-wise synthesis of CCD MVL functions","authors":"S. Zaky, Z. Vranesic, M. Abd-El-Barr","doi":"10.1109/ISMVL.1990.122637","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122637","url":null,"abstract":"A new approach for synthesis of single-variable functions in CCD (charge-coupled-device) technology is presented. It is based on primitive functions that rely heavily on the functions realizable with single overflow gates. Positive and negative steps in logic levels are decomposed into patterns realizable with the primitive functions. The resultant decomposition leads directly to a circuit realization. The approach is demonstrated on four-valued functions, but it can be extended to other radices.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Concerning the maximum size of the terms in the realization of symmetric functions 关于对称函数中项的最大大小的实现
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122636
J. Muzio
{"title":"Concerning the maximum size of the terms in the realization of symmetric functions","authors":"J. Muzio","doi":"10.1109/ISMVL.1990.122636","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122636","url":null,"abstract":"One method for realizing symmetric functions uses terms which consist of sums of fundamental symmetric functions. In many situations these sums simplify considerably. It is shown that, in the worst case, the size of these sums could approach half the number of possible fundamental symmetric functions without any simplification being possible. An expression for the number of fundamental symmetric functions is derived. For three- and four-valued systems, the size of the largest disjunction of fundamental symmetric functions is shown, and these results are extrapolated to the general case. It appears that the ratio between the maximum size and the total number of fundamental symmetric functions rapidly approaches one-half.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127007424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A neighborhood decoupling algorithm for truncated sum minimization 截断和最小化的邻域解耦算法
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122611
Chyan Yang, Yao-Ming Wang
{"title":"A neighborhood decoupling algorithm for truncated sum minimization","authors":"Chyan Yang, Yao-Ming Wang","doi":"10.1109/ISMVL.1990.122611","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122611","url":null,"abstract":"A heuristic, called the neighborhood decoupling (ND) algorithm, is described. It first selects a minterm and then selects an implicant, a two-step process employed in previous heuristics. The approach taken closely resembles the G.W. Dueck and D.M. Miller (1987) heuristic; however, it makes more efficient use of minterms truncated to the highest logic value. The authors present the algorithm, discuss its implementation, show that it performs consistently better than others, and explain the reason for its improved performance.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115104697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Properties of the Zhang-Hartley spectrum of patterns 图样的Zhang-Hartley谱的性质
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122595
C. Moraga, J. Poswig
{"title":"Properties of the Zhang-Hartley spectrum of patterns","authors":"C. Moraga, J. Poswig","doi":"10.1109/ISMVL.1990.122595","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122595","url":null,"abstract":"A relationship is developed between the 2-D Chrestenson transform and the 2-D Zhang-Hartley transform so that the computation of the Chrestenson spectrum can be reduced to real arithmetic. It is proved that the situation is similar to the well-known 1-D case, apart from some necessary permutations. Moreover, if the original function satisfies a specific decomposition condition, the relationship may be extended from the 1-D case to the 2-D case in a canonical way.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123031580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the synthesis of MVMT functions for PLA implementation using CCDs 用ccd实现PLA的MVMT函数的合成
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122639
M. Abd-El-Barr, H. Choy
{"title":"On the synthesis of MVMT functions for PLA implementation using CCDs","authors":"M. Abd-El-Barr, H. Choy","doi":"10.1109/ISMVL.1990.122639","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122639","url":null,"abstract":"A new programmable logic array (PLA) for implementation of multivalued multithreshold (MVMT) functions using charge-coupled-device (CCD) technology is introduced. It is shown that the number of functions realized using the proposed structure is larger than those realized using the authors' previously reported PLA structure. For example, all 256 four-valued three-threshold functions can be synthesized using only one column of the proposed PLA, as compared with two columns if the existing structure is used. This increase in functionality is achieved through increasing the number of gates per column from 8 to 12. The new structure exhibits the desirable feature of being dynamically reprogrammable at the user level by controlling the thresholds of the gates used. A synthesis procedure which can be used to synthesize MVMT functions for implementation using the proposed PLA is given.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114389338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Kleene-Stone logic functions 克莱恩-斯通逻辑函数
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122602
N. Takagi, M. Mukaidono
{"title":"Kleene-Stone logic functions","authors":"N. Takagi, M. Mukaidono","doi":"10.1109/ISMVL.1990.122602","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122602","url":null,"abstract":"Kleene algebra has correspondence with fuzzy sets or fuzzy logic and has recently been studied as an algebraic system treating ambiguity or fuzziness. In contrast, Stone algebra, which has connections with modality, has properties different from Kleene algebra. Kleene-Stone algebra has been proposed as an algebra that is both a Kleene algebra and a Stone algebra. A set of Kleene-Stone logic functions is one of the models of Kleene-Stone algebra. Fundamental properties, such as a quantization theorem for Kleene-Stone logic functions in which logic functions are determined by n-tuple vector spaces over (0, 1/4, 2/4, 3/4, 1), is clarified. The authors define a partial-order relation over (0, 1/4, 2/4, 3/4, 1), and then they show that any Kleene-Stone logic function satisfies the monotonicity for the partial-order relation. A canonical disjunctive form that enables them to represent any Kleene-Stone logic function uniquely is introduced.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116315854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fault detection in multiple valued logic circuits 多值逻辑电路的故障检测
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122596
T. Damarla
{"title":"Fault detection in multiple valued logic circuits","authors":"T. Damarla","doi":"10.1109/ISMVL.1990.122596","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122596","url":null,"abstract":"There are k=p/sup n/ different canonical representations for a given multiple-valued-logic (MVL) function, where k is called the polarity, and p and n denote the radix and the number of variables of a function, respectively. The coefficients in a canonical representation are called spectral coefficients. Relationships between the functional values of a function and the spectral coefficients are given. A relation between the number of spectral coefficients that a fault may distort and the number of test patterns required to detect the fault is given. It is also shown that the test patterns can be generated systematically.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126439326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Toward the age of beyond-binary electronics and systems 迈向超二进制电子和系统的时代
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122613
M. Kameyama
{"title":"Toward the age of beyond-binary electronics and systems","authors":"M. Kameyama","doi":"10.1109/ISMVL.1990.122613","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122613","url":null,"abstract":"The key issue in MVL (multiple-valued-logic) systems is the development of superior multiple-valued hardware algorithms and appropriate devices. From this point of view, several chips that are superior to the corresponding binary ones have been developed. These advantages will be greatly enhanced in the submicron geometry because performance depends on the interconnection resistance and capacitance. However, it will be necessary to evaluate these effects more formally and demonstrate their viability by actual VLSI implementations. Also, the basic research on MVL-oriented devices, such as biodevices, is essential to realize beyond-binary electronics and systems. The challenge for the 1990s will be to establish a significant role for MVL approaches in practical applications.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122304036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Some relationships between multiple-valued Kleenean functions and ternary input multiple-valued output functions 多值Kleenean函数与三元输入多值输出函数之间的一些关系
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122656
Y. Hata, K. Nakashima, K. Yamato
{"title":"Some relationships between multiple-valued Kleenean functions and ternary input multiple-valued output functions","authors":"Y. Hata, K. Nakashima, K. Yamato","doi":"10.1109/ISMVL.1990.122656","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122656","url":null,"abstract":"The multiple-valued Kleenean functions discussed are multiple-valued-logic functions represented by multiple-valued AND, OR, NOT, constants, and variables. First, when p=odd, ternary input p-valued output functions (or (3, p)-functions for short) are defined, and when p=even, ternary input (p+1)-valued output functions ((3, p+1)-functions for short) are defined by adding the value (p-1)/2. A derivation rule is proposed as a link between (3, p)-functions (or (3, p+1)-functions and p-valued (or (p+1)-valued) Kleenean functions. For p=odd, the mapping from monotonic (3,p)-functions to p-valued Kleenean functions is a bijection. For p=even, since the mapping from monotonic (3, p+1)-functions to p-valued Kleenean functions is not a bijection, a condition which makes the mapping a bijection is developed. Moreover, Kleenean functions with no constants are derived from B-ternary logic functions by the rule; then the mapping is a bijection.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
EXMIN: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued input two-valued output functions EXMIN:多值输入、二值输出函数的异或积和表达式的简化算法
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122597
Tsutomu Sasao
{"title":"EXMIN: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued input two-valued output functions","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.1990.122597","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122597","url":null,"abstract":"Minimization of AND-EXOR PLAs (programmable logic arrays) with input decoders corresponds to minimization of the number of products in exclusive-OR sum-of-products (ESOPs) expressions for multiple-valued-input, two-valued-output functions. A simplification algorithm for ESOPs, called EXMIN, is presented. The algorithm is based on an iterative improvement. Seven rules are used to replace one pair of products with another. Many AND-EXOR PLAs for arithmetic circuits are simplified. It is shown that in most cases AND-EXOR PLAs require fewer products than AND-OR PLAs.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114479649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 158
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