{"title":"Design of a high-density multiple-valued content-addressable memory based on floating-gate MOS devices","authors":"T. Hanyu, T. Higuchi","doi":"10.1109/ISMVL.1990.122586","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122586","url":null,"abstract":"A high-density, VLSI-oriented cellular associative memory for real-time numeric and nonnumeric computation is presented. Three kinds of basic search operations, which are parallel by word and serial by digit slice, are considered. A search word and memory words are encoded to several discrete values so that the number of digits to perform comparisons while searching can be greatly reduced. A multiple-valued down literal circuit of two variables, which is the basic building block for a compact content-addressable memory (CAM), can be implemented using a floating-gate MOS transistor whose threshold voltage is controllable by the external input signal. It is demonstrated that the number of transistors, cells, and interconnections between cells in an r-valued CAM are reduced to less than 1/log/sub 2/r in comparison with the corresponding binary implementation.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130255590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"4-valued BiCMOS circuits for the transmission system of a massively parallel architecture","authors":"D. Etiemble, C. Chanussot, V. Néri","doi":"10.1109/ISMVL.1990.122646","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122646","url":null,"abstract":"Two versions of four-valued encoder and decoder circuits using a BiCMOS technology are presented. A comparison is made of the performance of CMOS-only and BiCMOS versions of these circuits. Such circuits are intended for use in a four-valued transmission system in the 3D interconnection network of a massively parallel architecture. The main difference in performance between the two versions comes from the use of BiCMOS encoder circuits. As expected, the bipolar transistor that is used gives a significant reduction in chip area (from 20500 lambda /sup 2/ to 11300 lambda /sup 2/). For the entire transmission path, the BiCMOS version has an equivalent propagation delay for the evaluation phase and an improved delay for the precharge phase (3.8 ns instead of 13.2 ns). The total active chip area is reduced by 28%. The advantage of the BiCMOS encoder circuit comes from the decoupling of the process of generation of the four different levels realized by the MOS transistors and that of driving the high-capacitance load. BiCMOS technologies give new circuitry perspectives for four-valued off-chip transmission.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126007071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new CMOS gate-the balanced gate-for detecting physical failures","authors":"O. E. Katter, H. M. Razavi","doi":"10.1109/ISMVL.1990.122588","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122588","url":null,"abstract":"An approach to design-for-testability of CMOS logic circuits is presented. The method is based on design with a new family of gates, called balanced gates. These gates have an extra logic level that is used for testing. In the test mode, all the inputs to a gate are at 2.5 V, and if there are no faults the output would be at 2.5 V (gate is balanced). Circuits made with this family of gates require one test vector (2.5 V for each input) to achieve an acceptable level of fault detection. Simulation results indicate that circuits made from balanced gates are easily testable.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128340362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A six-valued logic for representing incomplete knowledge","authors":"O. N. Garcia, M. Moussavi","doi":"10.1109/ISMVL.1990.122605","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122605","url":null,"abstract":"A novel six-valued logic useful in representing incomplete knowledge is introduced. A practical advantage of this logic is that it allows a system to reason progressively about what it will or will not know (or what can or cannot happen) as time advances and further knowledge is acquired from the external world. Applications of this approach to deductive question-answering systems, as well as to decision-making and planning under time constraints, are investigated. A rule-based inference model based on the six valued logic has been built for this purpose. The results of this research indicate that an extension of the classical definition of modus ponens based on designated truth values would be a useful rule of inference.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126169454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A comparative analysis of multiplexer techniques for the minimization of function cost using the costtable approach (for costtable read cost-table)","authors":"J. T. Butler, H. Kerkhoff, S. Onneweer","doi":"10.1109/ISMVL.1990.122635","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122635","url":null,"abstract":"In the cost-table approach to logic design, a given function is realized by selecting functions from a table and combining them. Associated with each function is a cost, and the goal is to find, among all realizations, the one of least cost. An extension to the cost-table approach in which functions are combined using a multiplexer is shown, with the goal of finding an arrangement of the functions that yields the lowest cost. Specifically, an analysis is made of two techniques to minimize total function cost: (1) choosing which variables to apply to the multiplexer inputs, and (2) choosing a permutation of logic values that yields lowest cost. The relative benefits of (1), (2), and (1) and (2) together are analyzed. The basis of comparison is a set of randomly chosen two- and three-variable four-valued functions. It is shown that these techniques yield a reduction of 7% to 34% in the average cost over the use of a multiplexer without such techniques.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115444619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Bio-algebras","authors":"C. Reischer, D. Simovici","doi":"10.1109/ISMVL.1990.122592","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122592","url":null,"abstract":"A class of algebras which represent an extension of Boolean rings is introduced. The operations of these algebras are inspired by the work of M. Kameyama and T. Higuchi, and T. Aoki et al. (1989) biological computing, that is on computing based on the interactions between enzymes and substrata. A type of algebra that will be useful in the study of set-valued switching elements, as they occur in biocomputing, is introduced.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129864141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}