Proceedings of the Twentieth International Symposium on Multiple-Valued Logic最新文献

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Lukasiewicz logic arrays Lukasiewicz逻辑阵列
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122584
J. W. Mills, M. Beavers, Charles A. Daffinger
{"title":"Lukasiewicz logic arrays","authors":"J. W. Mills, M. Beavers, Charles A. Daffinger","doi":"10.1109/ISMVL.1990.122584","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122584","url":null,"abstract":"Lukasiewicz logic arrays (LLAs) are massively parallel analog computers organized as binary trees of identical processing elements performing either implication, negated implication, or both. The authors have designed and built working 31-cell CMOS VLSI LLA whose cells perform implication. They discuss the representation completeness of Lukasiewicz logic with respect to other multiple-valued logics; describe the architecture of the prototype LLA, its relationship to cellular automata and its VLSI implementation; show how the prototype LLA is programmed; and report on results obtained by programming the prototype LLA as a fuzzy function generator. Because LLAs have both an algebraic and a logical operational semantics, they can be used to implement approximate reasoning systems, including expert systems and neural networks.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120922433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
On the diagnosability of systems with three valued test results: diagnosis by comparison strategy 三值测试结果系统的可诊断性:比较诊断策略
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122606
A. Sengupta, C. Rhee
{"title":"On the diagnosability of systems with three valued test results: diagnosis by comparison strategy","authors":"A. Sengupta, C. Rhee","doi":"10.1109/ISMVL.1990.122606","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122606","url":null,"abstract":"A model of self-diagnosable multiprocessor systems, in which the faulty processors are determined by comparing the results of identical tasks performed by a pair of processors in the system, was introduced by J. Maeng and M. Malek (1981). An analysis is presented of the diagnosability problems for such a model when the result of comparison is three-valued. A set of criteria is given for determining whether the faulty processors in the system can be diagnosed on the basis of comparisons.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131488490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Note on resolution approximation of many-valued logics 关于多值逻辑的分辨率逼近的注意事项
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122622
Z. Stachniak
{"title":"Note on resolution approximation of many-valued logics","authors":"Z. Stachniak","doi":"10.1109/ISMVL.1990.122622","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122622","url":null,"abstract":"A discussion is presented of the problem of resolution approximation of many-valued logics, that is, the problem of defining propositional logics in terms of finite sets of resolution proof systems. The resolution proof systems discussed are based on the weak form of transformation rules. It is shown that for many-valued logics (and more generally, for resolution logics) minimal resolution approximations can be effectively constructed.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132389198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On design of multiple-valued static random-access-memory 多值静态随机存取存储器的设计
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122585
O. Ishizuka, Zheng Tang, H. Matsumoto
{"title":"On design of multiple-valued static random-access-memory","authors":"O. Ishizuka, Zheng Tang, H. Matsumoto","doi":"10.1109/ISMVL.1990.122585","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122585","url":null,"abstract":"General theories on multiple-valued static random-access memory (RAM) are investigated. The criteria for a stable and an unstable mode are proved with strict mathematical methods and expressed with diagrammatic representation. A circuit design and realization for NMOS six-transistor ternary and quaternary static RAM cells based on the theories are proposed and simulated with PSPICE. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5- mu m CMOS technology. Both PSPICE simulations and experiments indicate that the general theories presented are very useful and effective tools in optimal design and circuit realization of multiple-valued static RAMs.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"123 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114543091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Binary to quaternary encoding in clocked CMOS circuits using weak buffer 基于弱缓冲的CMOS电路二进制到四进制编码
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122617
D. Bhattacharya
{"title":"Binary to quaternary encoding in clocked CMOS circuits using weak buffer","authors":"D. Bhattacharya","doi":"10.1109/ISMVL.1990.122617","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122617","url":null,"abstract":"A binary-to-quaternary encoder is presented for four-valued signaling of buses in clocked CMOS integrated circuits. It uses a new CMOS circuit called the weak buffer. A weak buffer takes a conventional binary input and produces two stable output voltage levels of intermediate magnitudes that lie between the conventional 0 and 1 levels for binary circuits. Thus, the conventional binary voltage levels and the output levels of the weak buffer constitute a set of quaternary logic values. The encoder uses a binary-to-quaternary mapping different from the mappings used by other such encoder designs. Use of the new mapping and the weak buffer leads to 30%-56% savings in transistor count compared with previously reported designs. SPICE simulation results verifying its operation are presented. It is fairly insensitive to small variations in process parameters, and hence suitable for practical use. The circuit has been layed out using MAGIC and has been submitted to MOSIS for fabrication.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131474399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Application of multiple-valued switch-level algebra to the design and analysis of pass-transistor switch networks 多值开关级代数在通管开关网络设计与分析中的应用
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122620
Mou Hu, Kenneth C. Smith
{"title":"Application of multiple-valued switch-level algebra to the design and analysis of pass-transistor switch networks","authors":"Mou Hu, Kenneth C. Smith","doi":"10.1109/ISMVL.1990.122620","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122620","url":null,"abstract":"Pass-transistor switch networks have many advantages over gate-level networks, including high density, high speed, and low power dissipation. However, their design and analysis lack rigorous mathematical tools. A study is made of the application of the multiple-valued switch-level algebra introduced by M. Hu (1989) to the design and analysis of pass-transistor networks. After a brief introduction of the algebra, the design and analysis procedures are discussed in detail. Some design and analysis examples are given.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130514815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multi-valued neural logic networks 多值神经逻辑网络
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122658
L. Hsu, H. Teh, Sing-Chai Chan, K. Loe
{"title":"Multi-valued neural logic networks","authors":"L. Hsu, H. Teh, Sing-Chai Chan, K. Loe","doi":"10.1109/ISMVL.1990.122658","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122658","url":null,"abstract":"Two types of networks that are useful in developing expert systems are proposed. The probabilistic network can be used for predictive types of expert systems, whereas the fuzzy network is more suitable for expert systems that help in decision-making. In both cases, the expert system can operate in two modes. In the normal mode, rules are given by experts and weights are assigned values. In the learning mode, weights are allowed to vary while the system is fed with examples.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124665469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A general fuzzy logical operator set 一般模糊逻辑算子集
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122633
Lichun Cheng, Mou Hu
{"title":"A general fuzzy logical operator set","authors":"Lichun Cheng, Mou Hu","doi":"10.1109/ISMVL.1990.122633","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122633","url":null,"abstract":"A general basic fuzzy logical operator set is introduced. This set reserves many properties existing in binary logic. The set consists of four abstract operators: negation, conjunction, disjunctions, and implication. The authors discuss the fact that conjunction and implication are a pair of inverse operators, which is the foundation of the general set. By using this set in approximate reasoning, rule reappearance can occur, and the detachment domain (the set in which the detachment operation a V-product (a to b)=b holds) is the maximal that must be attained. Three important theorems are proved: the reasoning equivalent theorem, the condition of reproducing rule, and the maximal detachment domain theorem.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122210001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Walsh type transforms for completely and incompletely specified multiple-valued input binary functions 完全和不完全指定多值输入二元函数的Walsh类型变换
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122598
B. Falkowski, M. Perkowski
{"title":"Walsh type transforms for completely and incompletely specified multiple-valued input binary functions","authors":"B. Falkowski, M. Perkowski","doi":"10.1109/ISMVL.1990.122598","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122598","url":null,"abstract":"Spectral representation of multiple-valued input binary functions is proposed for the first time. Such a representation is composed of a vector of Walsh transforms, each of which is defined for one pair of the input variables of the function. The new representation has the advantage of being real valued and having, therefore, an easy interpretation. Since two types of binary function value codings are used, two different spectra are introduced. The meaning of each spectral coefficient is discussed in classical logic terms. The mathematical relationships between the number of true, false, and don't care minterms and spectral coefficients are stated. These relationships can be used to calculate the spectral coefficients directly from the graphical representations of binary functions. As do the spectral methods in classical logic design, the new spectral representation of binary functions find applications in many problems of analysis, synthesis, and testing of circuits described by such functions.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133941719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Minimization of functions with multiple-valued outputs: theory and applications 多值输出函数的最小化:理论与应用
Proceedings of the Twentieth International Symposium on Multiple-Valued Logic Pub Date : 1990-05-23 DOI: 10.1109/ISMVL.1990.122638
S. Devadas
{"title":"Minimization of functions with multiple-valued outputs: theory and applications","authors":"S. Devadas","doi":"10.1109/ISMVL.1990.122638","DOIUrl":"https://doi.org/10.1109/ISMVL.1990.122638","url":null,"abstract":"A theoretical framework for the minimization of logic functions with symbolic or multiple-valued outputs is presented. By use of this framework, efficient, exact algorithms for the problems of output encoding and finite-state-machine (FSM) state assignment are developed. All previous automatic approaches to these encoding problems have involved the use of heuristic techniques. A notion of generalized prime implicants is presented for functions with multiple-valued outputs, and a novel minimization procedure of prime implicant generation and covering for solving the output encoding problem is proposed. An optimum solution to this covering problem is also an optimum solution to the encoding problem. A single logic minimization step thus replaces on the order of n-factorial minimizations required by straightforward exhaustive search. It has been shown previously that the input encoding problem can be exactly solved using Boolean minimization over functions with multiple-valued inputs. An extension of the presented algorithm that handles functions with multiple-valued inputs and outputs can be used to solve the state assignment problem exactly. Experimental results are presented for a set of examples.<<ETX>>","PeriodicalId":433001,"journal":{"name":"Proceedings of the Twentieth International Symposium on Multiple-Valued Logic","volume":"4 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132397262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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