2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)最新文献_第6页

Worst case delay analysis for memory interference in multicore systems 多核系统中存储器干扰的最坏情况延迟分析

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456952

R. Pellizzoni, A. Schranzhofer, Jian-Jia Chen, M. Caccamo, L. Thiele

引用次数: 194

A black box method for stability analysis of arbitrary SRAM cell structures 用于任意 SRAM 单元结构稳定性分析的黑盒方法

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456943

M. Wieckowski, D. Sylvester, D. Blaauw, V. Chandra, Sachin Idgunji, C. Pietrzyk, R. Aitken

{"title":"A black box method for stability analysis of arbitrary SRAM cell structures","authors":"M. Wieckowski, D. Sylvester, D. Blaauw, V. Chandra, Sachin Idgunji, C. Pietrzyk, R. Aitken","doi":"10.1109/DATE.2010.5456943","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456943","url":null,"abstract":"Static noise margin analysis using butterfly curves has traditionally played a leading role in the sizing and optimization of SRAM cell structures. Heightened variability and reduced supply voltages have resulted in increased attention being paid to new methods for characterizing dynamic robustness. In this work, a technique based on vector field analysis is presented for quickly extracting both static and dynamic stability characteristics of arbitrary SRAM topologies. It is shown that the traditional butterfly curve simulation for 6T cells is actually a special case of the proposed method. The proposed technique not only allows for standard SNM “smallest-square” measurements, but also enables tracing of the state-space separatrix, an operation critical for quantifying dynamic stability. It is established via importance sampling that cell characterization using a combination of both separatrix tracing and butterfly SNM measurements is significantly more correlated to cell failure rates then using SNM measurements alone. The presented technique is demonstrated to be thousands of times faster than the brute force transient approach and can be implemented with widely available, standard design tools.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Instruction precomputation with memoization for fault detection 指令预计算与记忆的故障检测

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457081

D. Borodin, B. Juurlink

引用次数: 9

FPGA-based adaptive computing for correlated multi-stream processing 基于fpga的相关多流处理自适应计算

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456909

Ming Liu, Zhonghai Lu, W. Kuehn, A. Jantsch

引用次数: 7

Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors 多路冗余执行:芯片多处理器中一种高效容错技术

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457061

Pramod Subramanyan, Virendra Singh, K. Saluja, E. Larsson

引用次数: 28

Approximate logic synthesis for error tolerant applications 用于容错应用的近似逻辑综合

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456913

Doochul Shin, S. Gupta

{"title":"Approximate logic synthesis for error tolerant applications","authors":"Doochul Shin, S. Gupta","doi":"10.1109/DATE.2010.5456913","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456913","url":null,"abstract":"Error tolerance formally captures the notion that - for a wide variety of applications including audio, video, graphics, and wireless communications - a defective chip that produces erroneous values at its outputs may be acceptable, provided the errors are of certain types and their severities are within application-specified thresholds. All previous research on error tolerance has focused on identifying such defective but acceptable chips during post-fabrication testing to improve yield. In this paper, we explore a completely new approach to exploit error tolerance based on the following observation: If certain deviations from the nominal output values are acceptable, then we can exploit this flexibility during circuit design to reduce circuit area and delay as well as to increase yield. The specific metric of error tolerance we focus on is error rate, i.e., how often the circuit produces erroneous outputs. We propose a new logic synthesis approach for the new problem of identifying how to exploit a given error rate threshold to maximally reduce the area of the synthesized circuit. Experiment results show that for an error rate threshold within 1%, our approach provides 9.43% literal reductions on average for all the benchmarks that we target.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132660152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 187

Scalable codeword generation for coupled buses 耦合总线的可伸缩码字生成

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456954

Kedar Karmarkar, S. Tragoudas

引用次数: 9

Optimizing equivalence checking for behavioral synthesis 优化行为综合的等价性检验

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457049

K. Hao, Fei Xie, S. Ray, Jin Yang

引用次数: 30

Graphical Model Debugger Framework for embedded systems 嵌入式系统图形模型调试器框架

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457232

Kebin Zeng, Yu Guo, C. Angelov

引用次数: 11

Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs 精度自适应tlm并行仿真的建模结构和核

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456987

Rauf Salimi Khaligh, M. Radetzki

引用次数: 25