多路冗余执行:芯片多处理器中一种高效容错技术

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI:10.1109/DATE.2010.5457061

Pramod Subramanyan, Virendra Singh, K. Saluja, E. Larsson

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引用次数: 28

摘要

持续的CMOS缩放预计将使未来的微处理器容易受到瞬态故障，硬故障，制造缺陷和工艺变化的影响，导致容错变得非常重要，即使是针对商品市场的通用处理器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors

Continued CMOS scaling is expected to make future microprocessors susceptible to transient faults, hard faults, manufacturing defects and process variations causing fault tolerance to become important even for general purpose processors targeted at the commodity market.

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来源期刊

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)

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