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2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)最新文献

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Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits 在单通量量子(SFQ)电路实现的大规模数据路径加速器上映射科学应用
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456902
Farhad Mehdipour, H. Honda, H. Kataoka, Koji Inoue, I. Kataeva, K. Murakami, H. Akaike, A. Fujimaki
{"title":"Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits","authors":"Farhad Mehdipour, H. Honda, H. Kataoka, Koji Inoue, I. Kataeva, K. Murakami, H. Akaike, A. Fujimaki","doi":"10.1109/DATE.2010.5456902","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456902","url":null,"abstract":"To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is augmented to a general purpose processor to accelerate the execution of data flow graphs (DFGs) extracted from scientific applications. Procedure of mapping large DFGs onto the LSRDP is discussed and our proposed techniques for reducing area of the accelerator within the design procedure will be introduced as well.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125307073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Constrained Power Management: Application to a multimedia mobile platform 约束电源管理:在多媒体移动平台的应用
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456905
P. Bellasi, Stefano Bosisio, Matteo Carnevali, W. Fornaciari, D. Siorpaes
{"title":"Constrained Power Management: Application to a multimedia mobile platform","authors":"P. Bellasi, Stefano Bosisio, Matteo Carnevali, W. Fornaciari, D. Siorpaes","doi":"10.1109/DATE.2010.5456905","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456905","url":null,"abstract":"In this paper we provide an overview of CPM, a cross-layer framework for Constrained Power Management, and we present its application on a real use case. This framework involves different layers of a typical embedded system, ranging from device drivers to applications. The main goals of CPM are (i) to aggregate applications' QoS requirements and (ii) to exploit them to support an efficient coordination between different drivers' local optimization policies. This role is supported by a system-wide and multi-objective optimization policy which could be also changed at run-time. In this paper we mostly focus on a real use case to show the very low overhead of CPM both on the management of QoS requirements and on the tracking of hardware crossdependencies, which cannot be directly considered by local optimization policies.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125449562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Robust design of embedded systems 嵌入式系统的鲁棒设计
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457062
M. Lukasiewycz, M. Glaß, J. Teich
{"title":"Robust design of embedded systems","authors":"M. Lukasiewycz, M. Glaß, J. Teich","doi":"10.1109/DATE.2010.5457062","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457062","url":null,"abstract":"This paper presents a methodology to evaluate and optimize the robustness of an embedded system in terms of invariability in case of design revisions. Early decisions in embedded system design may be revised in later stages resulting in additional costs. A method that quantifies the expected additional costs as the robustness value is proposed. Since the determination of the robustness based on arbitrary revisions is computationally expensive, an efficient set-based approach that uses a symbolic encoding as Binary Decision Diagrams is presented. Moreover, a methodology for the integration of the optimization of the robustness into a design space exploration is proposed. Based on an external archive that accepts also near-optimal solutions, this robustness-aware optimization is efficient since it does not require additional function evaluations as previous approaches. Two realistic case studies give evidence of the benefits of the proposed approach.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125547287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Scenario-based analysis and synthesis of real-time systems using uppaal 基于场景的upal实时系统分析与综合
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457164
K. Larsen, Shuhao Li, B. Nielsen, Saulius Pusinskas
{"title":"Scenario-based analysis and synthesis of real-time systems using uppaal","authors":"K. Larsen, Shuhao Li, B. Nielsen, Saulius Pusinskas","doi":"10.1109/DATE.2010.5457164","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457164","url":null,"abstract":"We propose an automated, tool-supported approach to scenario-based analysis and synthesis of real-time embedded systems. The inter-object behaviors of a system are modeled as a set of live sequence charts (LSCs), and the scenario-based user requirement is specified as a separate LSC. By translating the set of LSC charts into a behavior-equivalent network of timed automata (TA), we reduce the problems of model consistency checking and property verification to classical CTL real-time model checking problems, and reduce the problem of centralized synthesis for open systems to a timed game solving problem. We implement a prototype LSC-to-TA translator, which can be linked to existing real-time model checker UPPAAL and timed game solver UPPAAL-TIGA. Preliminary experiments on a number of examples show that it is a viable approach.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126270460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
UML design for dynamically reconfigurable multiprocessor embedded systems 动态可重构多处理器嵌入式系统的UML设计
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5456989
Jorgiano Vidal, Florent de Lamotte, G. Gogniat, J. Diguet, Philippe Soulard
{"title":"UML design for dynamically reconfigurable multiprocessor embedded systems","authors":"Jorgiano Vidal, Florent de Lamotte, G. Gogniat, J. Diguet, Philippe Soulard","doi":"10.1109/DATE.2010.5456989","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456989","url":null,"abstract":"In this paper we propose a design methodology to explore partial and dynamic reconfiguration of modern FPGAs. We improve an UML based co-design methodology to allow dynamic properties in embedded systems. Our approach targets MPSoPC (Multiprocessor System on Programmable Chip) which allows area optimization through partial reconfiguration without performance penalty. In our case area reduction is achieved by reconfiguring co-processors connected to embedded processors. Most of the system is automatically generated by means of MDE techniques. Our modeling approach allows designers to target dynamic reconfiguration without being expert of modern FPGAs as many implementation details are hidden during the modeling step. Such a methodology allows design time speedup and a significant reduction of the gap between hardware and software modeling. In order to validate our approach, an object tracking application has been implemented on a reconfigurable system composed of 4 embedded processors and 3 co-processors. Dynamic reconfiguration has been performed for one co-processor which dynamically implements 3 different computations.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions 利用选择性负载值预测的SMT架构中的能源性能设计空间探索
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457197
A. Gellert, G. Palermo, V. Zaccaria, A. Florea, L. Vintan, C. Silvano
{"title":"Energy-performance design space exploration in SMT architectures exploiting selective load value predictions","authors":"A. Gellert, G. Palermo, V. Zaccaria, A. Florea, L. Vintan, C. Silvano","doi":"10.1109/DATE.2010.5457197","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457197","url":null,"abstract":"This paper presents a design space exploration of a selective load value prediction scheme suitable for energy-aware Simultaneous Multi-Threaded (SMT) architectures. A load value predictor is an architectural enhancement which speculates over the results of a micro-processor load instruction to speedup the execution of the following instructions. The proposed architectural enhancement differs from a classic predictor due to an improved selection scheme that allows to activate the predictor only when a miss occurs in the first level of cache. We analyze the effectiveness of the selective predictor in terms of overall energy reduction and performance improvement. To this end, we show how the proposed predictor can produce benefits (in terms of overall cost) when the cache size of the SMT architecture is reduced and we compare it with a classic non-selective load value prediction scheme. The experimental results have been gathered with a state-of-the-art SMT simulator running the SPEC2000 benchmark suite, both in SMT and non-SMT mode.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114267185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture MEDEA:一种混合的共享内存/消息传递多处理器基于noc的体系结构
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457237
S. Tota, M. Casu, M. R. Roch, Luca Rostagno, M. Zamboni
{"title":"MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture","authors":"S. Tota, M. Casu, M. R. Roch, Luca Rostagno, M. Zamboni","doi":"10.1109/DATE.2010.5457237","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457237","url":null,"abstract":"The shared-memory model has been adopted, both for data exchange as well as synchronization using semaphores in almost every on-chip multiprocessor implementation, ranging from general purpose chip multiprocessors (CMPs) to domain specific multi-core graphics processing units (GPUs). Low-latency synchronization is desirable but is hard to achieve in practice due to the memory hierarchy. On the contrary, an explicit exchange of synchronization tokens among the processing elements through dedicated on-chip links would be beneficial for the overall system performance. In this paper we propose the Medea NoC-based framework, a hybrid shared-memory/message-passing approach. Medea has been modeled with a fast, cycle-accurate SystemC implementation enabling a fast system exploration varying several parameters like number and types of cores, cache size and policy and NoC features. In addition, every SystemC block has its RTL counterpart for physical implementation on FPGAs and ASICs. A parallel version of the Jacobi algorithm has been used as a test application to validate the metodology. Results confirm expectations about performance and effectiveness of system exploration and design.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Towards a chip level reliability simulator for copper/low-k backend processes 面向铜/低k后端工艺的芯片级可靠性模拟器
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457195
M. Bashir, L. Milor
{"title":"Towards a chip level reliability simulator for copper/low-k backend processes","authors":"M. Bashir, L. Milor","doi":"10.1109/DATE.2010.5457195","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457195","url":null,"abstract":"A framework is proposed to analyze circuit layout geometries to predict chip lifetime due to low-k time-dependent dielectric breakdown (TDDB). The methodology uses as inputs data from test structures, which have been designed and fabricated to detect the impact of area and metal linewidth on low-k TDDB.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122527628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Recursion-driven parallel code generation for multi-core platforms 多核平台的递归驱动并行代码生成
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457214
R. Collins, Bharadwaj Vellore, L. Carloni
{"title":"Recursion-driven parallel code generation for multi-core platforms","authors":"R. Collins, Bharadwaj Vellore, L. Carloni","doi":"10.1109/DATE.2010.5457214","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457214","url":null,"abstract":"We present Huckleberry, a tool for automatically generating parallel implementations for multi-core platforms from sequential recursive divide-and-conquer programs. The recursive programming model is a good match for parallel systems because it highlights the temporal and spatial locality of data use. Recursive algorithms are used by Huckleberry's code generator not only to automatically divide a problem up into smaller tasks, but also to derive lower-level parts of the implementation, such as data distribution and inter-core synchronization mechanisms. We apply Huckleberry to a multi-core platform based on the Cell BE processor and show how it generates parallel code for a variety of sequential benchmarks.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131208077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Block-level bayesian diagnosis of analogue electronic circuits 模拟电路的块级贝叶斯诊断
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI: 10.1109/DATE.2010.5457100
Shaji Krishnan, Klaas D. Doornbos, Rudi Brand, H. Kerkhoff
{"title":"Block-level bayesian diagnosis of analogue electronic circuits","authors":"Shaji Krishnan, Klaas D. Doornbos, Rudi Brand, H. Kerkhoff","doi":"10.1109/DATE.2010.5457100","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457100","url":null,"abstract":"Daily experience with product designers, test and diagnosis engineers it is realized that the depth of interaction among them, ought be high for sucessfull diagnosis of analogue circuits. With this knowledge in mind, a responsibility was undertaken to choose a popular diagnostic method and define a systematic procedure that binds together the knowledge of a product from a design, test and diagnostic engineer. A set of software utilities was developed that assists in automating these procedures and in collecting appropriate data for effective diagnosis of analogue circuits. This paper will discuss the chosen methodology for diagnosis and the associated procedures for block-level diagnosis of analogue electronic circuits in detail. The paper is concluded with an illustration of the methodology and the related procedures of an industrial automotive voltage regulator circuit as a representative example.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126986959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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