面向铜/低k后端工艺的芯片级可靠性模拟器

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) Pub Date : 2010-03-08 DOI:10.1109/DATE.2010.5457195

M. Bashir, L. Milor

{"title":"面向铜/低k后端工艺的芯片级可靠性模拟器","authors":"M. Bashir, L. Milor","doi":"10.1109/DATE.2010.5457195","DOIUrl":null,"url":null,"abstract":"A framework is proposed to analyze circuit layout geometries to predict chip lifetime due to low-k time-dependent dielectric breakdown (TDDB). The methodology uses as inputs data from test structures, which have been designed and fabricated to detect the impact of area and metal linewidth on low-k TDDB.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"Towards a chip level reliability simulator for copper/low-k backend processes\",\"authors\":\"M. Bashir, L. Milor\",\"doi\":\"10.1109/DATE.2010.5457195\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A framework is proposed to analyze circuit layout geometries to predict chip lifetime due to low-k time-dependent dielectric breakdown (TDDB). The methodology uses as inputs data from test structures, which have been designed and fabricated to detect the impact of area and metal linewidth on low-k TDDB.\",\"PeriodicalId\":432902,\"journal\":{\"name\":\"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DATE.2010.5457195\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DATE.2010.5457195","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 21

摘要

提出了一种分析电路布局几何形状的框架，以预测由于低k时间相关介质击穿(TDDB)而导致的芯片寿命。该方法使用来自测试结构的输入数据，这些测试结构已被设计和制造，以检测面积和金属线宽对低k TDDB的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Towards a chip level reliability simulator for copper/low-k backend processes

A framework is proposed to analyze circuit layout geometries to predict chip lifetime due to low-k time-dependent dielectric breakdown (TDDB). The methodology uses as inputs data from test structures, which have been designed and fabricated to detect the impact of area and metal linewidth on low-k TDDB.

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来源期刊

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)

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