2015 International Conference on Communication Networks (ICCN)最新文献

Design of novel low power dynamic latch comparator using multi-Fin technology 基于多翅片技术的新型低功耗动态锁存比较器设计

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.22

Akanksha Singh, Aushi Marwah, S. Akashe

引用次数: 2

Design and analysis of switch mode power supply using CMOS single-phase full bridge rectifier 基于CMOS单相全桥整流器的开关电源设计与分析

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.72

Shubham Kumar, Prateek Jain, S. Akashe

{"title":"Design and analysis of switch mode power supply using CMOS single-phase full bridge rectifier","authors":"Shubham Kumar, Prateek Jain, S. Akashe","doi":"10.1109/ICCN.2015.72","DOIUrl":"https://doi.org/10.1109/ICCN.2015.72","url":null,"abstract":"This paper presents the design of a low leakage CMOS based switch mode power supply. The switch mode power supply converts the available deregulated A.C or D.C input supply to a regulated D.C output supply. This paper reviews the limitations of conventional linear regulated power supply and focuses on the advantages of switch mode power supply (SMPS) technique. The high frequency transformer used in the proposed circuit is much smaller in a size and weight compared to the low pitch transformer of the linear power supply circuit. The switching losses in modern switches like MOS are much lowered as compared to the loss in the linear element. The proposed circuit easily filtered the high frequency ripple produced in the circuit using smaller volumes of filtering elements. Leakage current, leakage power dissipation, average power dissipation and delay performance parameters are calculated. Due to simulation results, it is realized that the leakage current and power dissipation are reduced and delay is improved (reduced delay).The complete simulation and calculation method have been done in 45 nm technology at cadence virtuoso tool. The circuits were operated at 0.7v power supply.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123431406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Comparative analysis of AODV and DSR scalability in MANET MANET中AODV和DSR可扩展性的比较分析

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.15

C. Mafirabadza, P. Khatri, Reena Chauhan

引用次数: 3

The new multifin approach for mitigation of leakage in an Operational Transconductance Amplifier 运算跨导放大器中减少漏损的新多翅片方法

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.63

Prateek Tiwari, R. S. Tomar, S. Akashe

引用次数: 0

Design and optimization of narrow band low noise amplifier using 0.18µm CMOS 0.18µm CMOS窄带低噪声放大器的设计与优化

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.21

Hasmukh P. Koringa, V. Shah

引用次数: 3

Convolution coding and applications: A performance analysis under AWGN channel 卷积编码及其应用:AWGN信道下的性能分析

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.17

Rinu Ann Baby

引用次数: 4

Performance and analysis of 10T Full Adder using MTCMOS technique 采用MTCMOS技术的10T全加法器性能及分析

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.56

V. Agarawal, Ravindra Shrivastava, S. Akashe

{"title":"Performance and analysis of 10T Full Adder using MTCMOS technique","authors":"V. Agarawal, Ravindra Shrivastava, S. Akashe","doi":"10.1109/ICCN.2015.56","DOIUrl":"https://doi.org/10.1109/ICCN.2015.56","url":null,"abstract":"Full Adder performs addition and therefore in microprocessor and digital signal processor, it is used for arithmetic operation, for comparison and for access the address in memory. Improvement of this circuit would impart a greater impact on the performance of large systems where it has been employed. For improvement of power and delay performance in full adder, the 10T structure based static energy recovery type full Adder (SERF) has been utilized with MTCMOS technique at 45nm technology. MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technique has been emerged as a promising and popular circuit technique for further improvement in performance (i.e. reduction in delay and power minimization) of full adder. The paper here illustrates the analysis of leakage current, active power, delay and noise with power supply of (0.7 V). The reduction in power consumption in the structure represented is computed as 90.27nW and propagation delay of 10.24ns, which significantly improves and makes the circuit more efficient and reliable. The leakage current has been reduced and lies between 1.004-1.771pA with different supply voltages from 0.5v to 0.9v. The adder has been analyzed for various parameters. All simulation results are performed with 45nm CMOS technology, 20ns access time and 0.05GHZ frequency using cadence virtuoso tool.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127814614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Neural signal front-end amplifier in 45 nm technology 45纳米技术的神经信号前端放大器

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.43

Jainendra Tripathi, R. S. Tomar, S. Akashe

引用次数: 2

Analysis and performance improvement of K-means clustering in big data environment 大数据环境下K-means聚类分析及性能改进

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.9

Purva Rathore, Deepak Shukla

{"title":"Analysis and performance improvement of K-means clustering in big data environment","authors":"Purva Rathore, Deepak Shukla","doi":"10.1109/ICCN.2015.9","DOIUrl":"https://doi.org/10.1109/ICCN.2015.9","url":null,"abstract":"The big data environment is used to support the huge amount of data processing. In this environment tons (i.e. Giga bytes, Tera bytes) of data is processed. Therefore the various online applications where the huge data request are generated are treated using the big data i.e. facebook, google. In this presented work the big data environment is studied and investigated how the data is consumed using the big data and how the supporting tools are working with the Hadoop storage. Furthermore, for keen understanding and investigation, a cluster analysis technique more specifically the K-mean clustering algorithm is implemented through the Hadoop and MapReduce. The clustering is a part of big data analytics where the unlabelled data is processed and utilized to make groups of the data. In addition of that it is observed the traditional k-mean algorithm is not much suitably works with the Hadoop and MapReduce thus small amount of modification is performed on the data processing technique. In addition of that during cluster analysis various issues are found in traditional k-means i.e. fluctuating accuracy, outliers and empty cluster. Therefore a new clustering algorithm with modification on traditional approach of k-means clustering is proposed and implemented. That approach first enhances the data quality by removing the outlier points in datasets and then the bi-part method is used to perform the clustering. The proposed clustering technique implemented using the JAVA, Hadoop and MapReduce finally the performance of the proposed clustering approach is evaluated and compared with the traditional k-means clustering algorithm. The obtained performance shows the effective results and enhanced accuracy of cluster formation with the removal of the de-efficiency. Thus the proposed work is adoptable for the big data environment with improving the performance of clustering.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123452858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Low power application for nano scaled Memristor based 2∶1 multiplexer 基于2∶1多路复用器的纳米忆阻器的低功耗应用

2015 International Conference on Communication Networks (ICCN) Pub Date : 2015-11-01 DOI: 10.1109/ICCN.2015.7

Arpana Verma, S. Akashe

{"title":"Low power application for nano scaled Memristor based 2∶1 multiplexer","authors":"Arpana Verma, S. Akashe","doi":"10.1109/ICCN.2015.7","DOIUrl":"https://doi.org/10.1109/ICCN.2015.7","url":null,"abstract":"Now a day market demands compressed devices that operates on low voltage and causes less noise in the output. Advanced nano scale very large integrated circuits are facing significant timing closure challenges especially due to random on chip threshold voltage variations. Memristor can play an important role in improving the scalability and efficiency of existing memory technology. Accordingly this article introduces Memristor based 2:1 multiplexer. Memristor is non linear passive two terminal electrical components relating electric charge. Memristor has dynamic relationship between current and voltage including a memory of past voltage or current. In this paper two main properties of Memristor is highlighted firstly nano scale dimension and another it's non volatile memory characteristics. By using these properties it gives better way to design the circuit as well as it stored output too. With the many advantages of Memristor CMOS it becomes possible to reduce the area on silicon chip. Here many CMOS transistors are replaced by few Memristor and multiplexer is made. All related parameters of multiplexer, are calculated in the cadence virtuoso tool and 45nm technology with 0.7 v operating voltage.","PeriodicalId":431743,"journal":{"name":"2015 International Conference on Communication Networks (ICCN)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126196810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5