Design of novel low power dynamic latch comparator using multi-Fin technology

Abstract

The designing of high speed (ADC) analog to digital converter in low power for improving the performance like speed and power efficiency in dynamic latch comparator. This paper deals in reduction of leakage power and propagation delay of this dynamic latch comparator. Using various techniques designers can simulate and observe the different factors for enhancing the performance of the circuit. The conventional circuit is modified by using FinFET technique and with the help of proposed circuit the performance of the comparator circuit is enhanced. Performance parameters of the comparator like average power dissipation, energy efficiency, delay are being improved by using FinFET technique as compared to that of the conventional comparator circuit. Leakage power obtained using FinFET is 56.84 pW which is very less than that of conventional comparator. Simulation is done in 45-nm CMOS technology which confirms the analysis results.