Performance and analysis of 10T Full Adder using MTCMOS technique

Abstract

Full Adder performs addition and therefore in microprocessor and digital signal processor, it is used for arithmetic operation, for comparison and for access the address in memory. Improvement of this circuit would impart a greater impact on the performance of large systems where it has been employed. For improvement of power and delay performance in full adder, the 10T structure based static energy recovery type full Adder (SERF) has been utilized with MTCMOS technique at 45nm technology. MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technique has been emerged as a promising and popular circuit technique for further improvement in performance (i.e. reduction in delay and power minimization) of full adder. The paper here illustrates the analysis of leakage current, active power, delay and noise with power supply of (0.7 V). The reduction in power consumption in the structure represented is computed as 90.27nW and propagation delay of 10.24ns, which significantly improves and makes the circuit more efficient and reliable. The leakage current has been reduced and lies between 1.004-1.771pA with different supply voltages from 0.5v to 0.9v. The adder has been analyzed for various parameters. All simulation results are performed with 45nm CMOS technology, 20ns access time and 0.05GHZ frequency using cadence virtuoso tool.