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Evaluation of the vertical magnetic field generated by a spiral planar coil 螺旋平面线圈产生的垂直磁场的评价
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364379
B. Minnaert, N. Stevens
{"title":"Evaluation of the vertical magnetic field generated by a spiral planar coil","authors":"B. Minnaert, N. Stevens","doi":"10.1109/NORCHIP.2015.7364379","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364379","url":null,"abstract":"The study of the magnetic field generated by planar spiral coils is important in several widespread application domains. However, calculating this magnetic field distribution is complex and requires expensive computational electromagnetic (CEM) tools. In this paper, we reduce this challenge to the evaluation of a single integral for the vertical field component for a general, planar spiral coil. We focus on the vertical field component due to its importance in most applications such as wireless power transfer. We verify our calculations by comparing them with the simulation results from the CEM tool `CST EM Studio'. Our results make it possible to quickly determine this field with any standard mathematical software package, thus without the need for an expensive CEM tool.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125839477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems LTE和OFDM系统的intel处理器和Xeon phi并行独立FFT实现
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364402
M. Khelifi, D. Massicotte, Y. Savaria
{"title":"Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems","authors":"M. Khelifi, D. Massicotte, Y. Savaria","doi":"10.1109/NORCHIP.2015.7364402","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364402","url":null,"abstract":"Fast Fourier Transform (FFT) is a key element for wireless applications based on the OFDM (Orthogonal Frequency Division Multiplexing) and challenging for implementing on processor multi-cores/many-cores. As an example, the Long Term Evolution (LTE) protocol establishes a requirement for processing, whereby many independent FFTs must be calculated within a limited time slot. By using Intel Math Kernel Library (MKL), in our approach to Xeon phi, we managed to reduce the maximum execution time of many independent FFTs. We proposed an implementation on processors multi-cores/many-cores using OpenMP (Open Multi-processing) reducing the mean time latency to 124 μs on native mode after 1300 μs with the offload. This is a challenge for shared memory projects. This paper describes how this level of performance can be obtained with multi-core Intel i7, Xeon processors and a many-core Xeon Phi. The best results were obtained with the Xeon Phi, which outperformed the Xeon Sandy-Bridge.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133681267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
System level design of a continuous-time ΔΣ modulator for portable ultrasound scanners 便携式超声扫描仪连续时间ΔΣ调制器的系统级设计
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364408
Pere Llimós Muntal, Kjartan Færch, I. Jørgensen, Erik Bruun
{"title":"System level design of a continuous-time ΔΣ modulator for portable ultrasound scanners","authors":"Pere Llimós Muntal, Kjartan Færch, I. Jørgensen, Erik Bruun","doi":"10.1109/NORCHIP.2015.7364408","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364408","url":null,"abstract":"In this paper the system level design of a continuous-time ΔΣ modulator for portable ultrasound scanners is presented. The overall required signal-to-noise ratio (SNR) is derived to be 42 dB and the sampling frequency used is 320MHz for an oversampling ratio of 16. In order to match these requirements, a fourth order, 1-bit modulator with optimal zero placing is used. An analysis shows that the thermal noise from the resistors and operational transconductance amplifier is not a limiting factor due to the low required SNR, leading to an inherently very low-power implementation. Furthermore, based on high-level VerilogA simulations, the performance of the ΔΣ modulator versus various block performance parameters is presented as trade-off curves. Based on these results, the block specifications are derived.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117182531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test-driven modeling of embedded systems 嵌入式系统的测试驱动建模
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364410
A. Munck, J. Madsen
{"title":"Test-driven modeling of embedded systems","authors":"A. Munck, J. Madsen","doi":"10.1109/NORCHIP.2015.7364410","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364410","url":null,"abstract":"To benefit maximally from model-based systems engineering (MBSE) trustworthy high quality models are required. From the software disciplines it is known that test-driven development (TDD) can significantly increase the quality of the products. Using a test-driven approach with MBSE may have a similar positive effect on the quality of the system models and the resulting products and may therefore be desirable. To define a test-driven model-based systems engineering (TD-MBSE) approach, we must define this approach for numerous sub disciplines such as modeling of requirements, use cases, scenarios, behavior, architecture, etc. In this paper we present a method that utilizes the formalism of timed automatons with formal and statistical model checking techniques to apply TD-MBSE to the modeling of system architecture and behavior. The results obtained from applying it to an industrial case suggest that our method provides a sound foundation for rapid development of high quality system models.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116514852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A capacitor-free, fast transient response linear voltage regulator in a 180nm CMOS 180nm CMOS无电容、快速瞬态响应线性稳压器
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364358
Alexander N. Deleuran, Nicklas Lindbjerg, Martin K. Pedersen, Pere Llimós Muntal, I. Jørgensen
{"title":"A capacitor-free, fast transient response linear voltage regulator in a 180nm CMOS","authors":"Alexander N. Deleuran, Nicklas Lindbjerg, Martin K. Pedersen, Pere Llimós Muntal, I. Jørgensen","doi":"10.1109/NORCHIP.2015.7364358","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364358","url":null,"abstract":"A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 μm CMOS process. The design has a low component count and is tailored for system-on-chip integration. A current step load from 0-50 mA with a rise time of 1 μs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121268155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Architectural design space exploration of an FPGA-based compressed sampling engine: Application to wireless heart-rate monitoring 基于fpga的压缩采样引擎的架构设计空间探索:在无线心率监测中的应用
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364369
Mohammad El-Sayed, P. Koch, Y. Moullec
{"title":"Architectural design space exploration of an FPGA-based compressed sampling engine: Application to wireless heart-rate monitoring","authors":"Mohammad El-Sayed, P. Koch, Y. Moullec","doi":"10.1109/NORCHIP.2015.7364369","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364369","url":null,"abstract":"We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133820892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs 通过非对称3d - noc的缓冲重组为异构3d - soc节省面积和功耗
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364370
J. Joseph, Christopher Blochwitz, Thilo Pionteck, A. Ortiz
{"title":"Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs","authors":"J. Joseph, Christopher Blochwitz, Thilo Pionteck, A. Ortiz","doi":"10.1109/NORCHIP.2015.7364370","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364370","url":null,"abstract":"In this paper, optimizations for asymmetric Network-on-Chip (NoC) router architectures are proposed for heterogeneous 3D-System-on-Chips (SoCs). The optimizations cover buffer reorganization among dies and focus on power and area savings. The architectures are compared to conventional, symmetric routers on the bases of synthesizable RTL models. Area savings of 8.3% and power savings of 5.4% for link buffers are achieved while accepting a minor average system performance loss of 2.1% in simulations. We thereby demonstrate the potentials of asymmetric NoC designs for heterogeneous 3D-SoCs.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134010559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low power unrolled CORDIC architectures 低功耗展开CORDIC架构
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364396
P. Nilsson, Yuhang Sun, Rakesh Gangarajaiah, E. Hertz
{"title":"Low power unrolled CORDIC architectures","authors":"P. Nilsson, Yuhang Sun, Rakesh Gangarajaiah, E. Hertz","doi":"10.1109/NORCHIP.2015.7364396","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364396","url":null,"abstract":"This paper shows a novel methodology to improve unrolled CORDIC architectures. The methodology is based on removing adder stages starting from the first stage. As an example, a 19-stage CORDIC is used but the methodology is applicable on CORDICs with an arbitrary number of stages. The CORDIC is implemented, simulated, and synthesized into hardware. In the paper, the performance is shown to be increased by 23% and that the dynamic power can be reduced by 27%.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131643927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of spread-spectrum techniques to class-E DC/DC converters: some preliminary results 扩频技术在e类DC/DC变换器中的应用:一些初步结果
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364368
Fabio Pareschi, Tommaso Vincenzi, Mauro Mangia, Nicola Bertoni, R. Rovatti, G. Setti
{"title":"Application of spread-spectrum techniques to class-E DC/DC converters: some preliminary results","authors":"Fabio Pareschi, Tommaso Vincenzi, Mauro Mangia, Nicola Bertoni, R. Rovatti, G. Setti","doi":"10.1109/NORCHIP.2015.7364368","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364368","url":null,"abstract":"Spread spectrum clocking (SSC) has recently emerged as a very effective solution to mitigate electromagnetic interference (EMI) issues. In last years it has been widely used in switching dc/dc converters, in particular in class-D ones, i.e., that based on pulse-width modulation. Conversely, it finds no application in resonant ones. Within this paper we investigate the effects of applying SSC techniques to a recently introduced resonant class-E converter. Intensive SPICE simulations using both basic and advanced SSC techniques show not only that SSC is effective in mitigating EMI issues in this class of converters, but also that the most important circuit figures of merit such as conversion efficiency are not affected.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114718108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm 分支和绑定流水车间调度算法的硬件体系结构
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364362
Mikhael Daouri, Fernando A. Escobar, Xin Chang, C. Valderrama
{"title":"A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm","authors":"Mikhael Daouri, Fernando A. Escobar, Xin Chang, C. Valderrama","doi":"10.1109/NORCHIP.2015.7364362","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364362","url":null,"abstract":"Branch-and-Bound (B&B) algorithms are one of the most employed techniques in optimization problems. Its complexity increases exponentially with problem size and features a challenging dynamic memory management caused by recursive processing. Most solutions focus on parallel branch evaluation in multi-core CPUs or GPUs. To the best of our knowledge, to the date, no works have employed FPGAs to implement the BB technique. In this paper, we propose a mixed hardware-software architecture to solve the Flow-Shop Scheduling Problem (FSP). We use Vivado HLS to construct a simple processing element (PE) for lower bound computation and integrate it with an ARM processor system. A Xilinx ZYNQ-7020 device is used to synthesize 10 PEs and reach an acceleration of about 5× over bare-metal execution on the same platform. In addition, we propose a pseudo-branching technique for higher computation overlapping attaining speed ups of 10.3× for a maximum problem size of 20 jobs in 20 machines.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116312125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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