2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)最新文献

How small and still effective a CMOS-SoC could ever be? CMOS-SoC能有多小、多有效?

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364390

H. Heusala, J. Skyttä

{"title":"How small and still effective a CMOS-SoC could ever be?","authors":"H. Heusala, J. Skyttä","doi":"10.1109/NORCHIP.2015.7364390","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364390","url":null,"abstract":"In this paper, effects of expected physical limits of CMOS technology on the performance of small-scale System-on-Chips (SoCs) are described. The exponential progress of CMOS technology has entered to the saturation phase. This could be called, if we like, a third phase of the Moore's law. In this third phase of development, the peak-performance of SoCs is not any more in the main concern. Instead of that, we could see an explosion of creative small-size applications: bionic appendages, smartphones with smart sensors, networks of tiny sensors, and a host of other applications we have yet to imagine. The International Technology Roadmap for Semiconductors (ITRS) lists expected performance parameters for CMOS technology up to the year 2028. In this paper, it is shown that starting from the simple RTL architecture parameters, e.g., gate count, and using performance figures taken from ITRS, we are able to figure out the (space-time-energy) performance limits of CMOS implementation of any logic architecture. As a practical example, the study of performance limits of a novel digital receiver suitable to be used in different capillary networks of Internet-of-Things applications is described, here. Design space exploration technique described in this paper can be used to find out performance limits of wide range of smart object applications.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124819211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A CMOS High Resolution Multi-Edge Delay Generator CMOS高分辨率多边延迟发生器

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364359

S. Harb, W. Eisenstadt

引用次数: 3

Long-Term ECG monitoring with zeroing Compressed Sensing approach 基于零化压缩感知方法的长期心电监测

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364394

Mauro Mangia, Daniele Bortolotti, Andrea Bartolini, Fabio Pareschi, L. Benini, R. Rovatti, G. Setti

引用次数: 5

A low/high band highly linearized reconfigurable down conversion mixer in 65nm CMOS process 一种低/高频带高度线性化、可重构的65nm CMOS下变频混频器

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364363

N. Gupta, A. Dutta, S. Singh

{"title":"A low/high band highly linearized reconfigurable down conversion mixer in 65nm CMOS process","authors":"N. Gupta, A. Dutta, S. Singh","doi":"10.1109/NORCHIP.2015.7364363","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364363","url":null,"abstract":"This paper presents a universal down conversion mixer for a multistandard wireless receiver with adapted reconfigurability in the form of RF bandwidth, active/passive and IF bandwidth. In the proposed architecture RF bandwidth reconfigurability is reconfigured between low band (LB) RF frequency and high band (HB) RF frequency mixer modes. LB / HB reconfigurability is made through power switching the transconductance amplifier. Active / Passive reconfigurability is made through switching the input signal between gate and source terminal of input transistors and enabling/disabling the transimpedance stage at the output. The CMOS transmission gate (TG) switches are designed to provide optimum headroom in this low voltage design. The proposed circuit is designed in the UMC 65nm RFCMOS technology with 1.2V supply voltage. From the simulation results, the proposed circuit shows conversion gain of 22/26 dB and 25/31 dB, noise figure of 14.2/12.1 dB and 11.5/8.16 dB, IIP3 of 10/8.1 dBm and 6.4/3 dBm in LB and HB respectively where all these figures suggest passive/active mode. Hence this circuit will be much helpful in multi-standard receiver design.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"48 5 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128203896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter bw跟踪半数字锁相环，在低成本0.4µm CMOS中具有接近最佳的压控振荡器相位噪声整形，实现700fs rms的相位抖动

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364357

S. Fahmy, M. Dietl, P. Sareen, M. Ortmanns, J. Anders

{"title":"A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter","authors":"S. Fahmy, M. Dietl, P. Sareen, M. Ortmanns, J. Anders","doi":"10.1109/NORCHIP.2015.7364357","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364357","url":null,"abstract":"This paper presents a low-power BW-tracking semi-digital PLL. The design features independently adjustable proportional and integral controller paths. The digital information provided by the storage cells in the I-path are used to let the PLL bandwidth and phase margin track the VCO frequency. The proposed switching scheme in the P-path provides a quiet output in the locked state significantly reducing update jitter. In contrast to classical analog charge pump PLLs, the proposed concept features low design complexity and small area requirements and does not require external components. In contrast to digital PLLs, the proposed architecture allows for an excellent phase noise performance without the need for highly scaled CMOS technologies. As a proof-of-concept of the proposed architecture, a PLL prototype realized in a low cost 0.4 μm CMOS technology is presented, which achieves a measured integrated rms jitter of only 700 fs competing with the state-of-the-art in deep submicron CMOS technologies.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134187450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Secured-by-design FPGA: look-up tables and switch-boxes 设计安全的FPGA:查找表和开关盒

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364404

Z. Almohaimeed, M. Sima

引用次数: 3

Carrier frequency and sampling rate offsets effect on sub 6 GHz Massive MIMO 载波频率和采样率偏移对6ghz以下大规模MIMO的影响

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364371

M. Ahmed-Ouameur, D. Massicotte, Weiping Zhu

{"title":"Carrier frequency and sampling rate offsets effect on sub 6 GHz Massive MIMO","authors":"M. Ahmed-Ouameur, D. Massicotte, Weiping Zhu","doi":"10.1109/NORCHIP.2015.7364371","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364371","url":null,"abstract":"Hardware impairments effects on Massive MIMO system's capacity were investigated and seem to vanish asymptotically at the base station when equipped with a larger array. Surprisingly, the effect of the local oscillator (LO) phase noise does not strictly obey the same law as the additive noise when a common LO is utilized. Having a close look at large array base station utilizing OFDM signaling, one would expect that the sampling rate and carrier frequency offsets (SRO and CFO) to introduce similar effects as the phase noise due to the time (subcarriers and OFDM symbols indices) dependence of the channel vector's phase terms. For practical reasons, we use simulation to investigate the effect of such offsets on massive MIMO utilizing low computational complexity precoding techniques such as conjugate beamforming (CBF) and zero forcing beamforming (ZFBF). A reduced computational complexity ZFBF utilizing polynomial expansion technique is considered to assess sensitivity to such offsets. The simulation results show that without accurate compensation or calibration methods, the effect of sampling rate and carrier frequency offsets is very dramatic on massive MIMO performance. Increasing the array size does not provide an economically viable solution to alleviate the negative effects of such offsets.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131719174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Microcontroller energy consumption estimation based on software analysis for embedded systems 基于软件分析的嵌入式系统单片机能耗估算

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364397

P. Ruberg, Keijo Lass, P. Ellervee

引用次数: 10

Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs 开关电容放大器1.1dB-IL三阶匹配网络的分析与设计

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364367

A. Passamani, D. Ponton, G. Knoblinger, A. Bevilacqua

引用次数: 7

Adaptive Power monitoring for self-aware embedded systems 自感知嵌入式系统的自适应电源监测

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364364

Mohamad El Ahmad, M. Najem, P. Benoit, G. Sassatelli, L. Torres

引用次数: 4