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Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits 加速数字电路并行模式仿真的共享结构合成bdd
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364406
R. Ubar, Lembit Jurimagi, J. Raik
{"title":"Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits","authors":"R. Ubar, Lembit Jurimagi, J. Raik","doi":"10.1109/NORCHIP.2015.7364406","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364406","url":null,"abstract":"Fault simulation is a critical tool in design, analysis of testability and verification of circuits. BDDs are a well-known model for manipulating Boolean functions. We propose a new type of BDD in the form of Shared Structurally Synthesized BDD (S3BDD) for representing the structure and simulating of faults in digital circuits. The paper offers a formula for calculating the minimal size, a method for synthesis of S3BDDs and a method for parallel pattern simulation with S3BDDs. We demonstrate a considerable increase in the speed-up of simulation of digital circuits using S3BDDs.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131654650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fault-tolerant implementation of direct FIR filters protected using residue codes 使用剩余代码保护的直接FIR滤波器的容错实现
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364382
S. Piestrak, Piotr Patronik
{"title":"Fault-tolerant implementation of direct FIR filters protected using residue codes","authors":"S. Piestrak, Piotr Patronik","doi":"10.1109/NORCHIP.2015.7364382","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364382","url":null,"abstract":"The design of fault-secure and fault-tolerant versions of digital finite input response (FIR) filters implemented in direct form is studied. The fault-secure versions proposed are protected using residue codes mod A (A is an odd integer) and guarantee the 100% error coverage for all single line faults, should some elementary design rules be respected. The fault-tolerant versions rely on duplication of fault-secure versions. The synthesis results suggest that the hardware overhead needed could be also as low as for their transposed versions counterparts proposed recently: for all fault-secure filters with 16-bit operands and protected using the residue code mod 3 it is about 3%. For fault-tolerant versions with 16-bit operands, the hardware overhead ranges only from about 105 to 117.5%, which is significantly less than over 200% for triplication.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129586189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Two-variable numeric function approximation using least-squares-based regression 使用基于最小二乘回归的双变量数值函数近似
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364413
Jochen Rust, N. Heidmann, S. Paul
{"title":"Two-variable numeric function approximation using least-squares-based regression","authors":"Jochen Rust, N. Heidmann, S. Paul","doi":"10.1109/NORCHIP.2015.7364413","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364413","url":null,"abstract":"Automated design of two-variable numeric functions can be realized efficiently by extending well-known multiplier-less linear function approximation techniques; the arithmetic signal processing effort is minimized by the utilization of a non-uniform piecewise segmentation scheme. However, as common state-of-the-art approaches only consider unpretentious coefficient estimation techniques, such as gradient superposition, this results in large multiplexer-trees for segmentation that, consequently, are restricting the total performance. In this paper a least-squares-based estimation of multiplier-less linear coefficients is introduced that minimizes the number of segments by using a least-squares-based coefficient estimation. The evaluation indicates a reduction of the segmentation effort by nearly 31% on average. Logical and physical CMOS synthesis is performed and the results are compared to actual references highlighting our work high performance approach for the hardware-based calculation of two-variable numeric functions.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132079440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fault tolerant Field Programmable Neural Networks 容错现场可编程神经网络
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364381
Martin Krcma, Z. Kotásek, Jan Kastil
{"title":"Fault tolerant Field Programmable Neural Networks","authors":"Martin Krcma, Z. Kotásek, Jan Kastil","doi":"10.1109/NORCHIP.2015.7364381","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364381","url":null,"abstract":"This paper describes a concept of Field Programmable Neural Networks (FPNNs) for artificial neural networks implementation in FPGAs, presents a model of fault tolerant FPNNs and different fault tolerance improving techniques based on the model. It describes an experiment based on one of these techniques and presents its results.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133645717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias 采用正向体偏置的28 nm UTBB FDSOI CMOS超低电压OTA
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364416
P. Harikumar, J. Wikner, A. Alvandpour, J. Wikner, A. Alvandpour
{"title":"An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias","authors":"P. Harikumar, J. Wikner, A. Alvandpour, J. Wikner, A. Alvandpour","doi":"10.1109/NORCHIP.2015.7364416","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364416","url":null,"abstract":"This paper presents an ultra-low-voltage, sub-μW fully differential operational transconductance amplifier (OTA) designed in 28 nm ultra-thin buried oxide (BOX) and body (UTBB) fully-depleted silicon-on-insulator (FDSOI) CMOS process. In this CMOS process, the BOX isolates the substrate from the drain and source and hence enables a wide range of body bias voltages. Extensive use of forward body biasing has been utilized in this work to reduce the threshold voltage of the devices, boost the device transconductance (gm) and improve the linearity. Under nominal process and temperature conditions at a supply voltage of 0.4 V, the OTA achieves -64 dB of total harmonic distortion (THD) with 75% of the full scale output swing while consuming 785 nW. The two-stage OTA incorporates continuous-time common-mode feedback circuits (CMFB) and achieves DC gain = 72 dB, unity-gain frequency of 2.6 MHz and phase margin of 68°. Sufficient performance is maintained over process, supply voltage and temperature variations.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116258615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Interfacing hardware accelerators to a time-division multiplexing network-on-chip 将硬件加速器连接到片上时分多路网络
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364392
Luca Pezzarossa, R. B. Sorensen, Martin Schoeberl, J. Sparsø
{"title":"Interfacing hardware accelerators to a time-division multiplexing network-on-chip","authors":"Luca Pezzarossa, R. B. Sorensen, Martin Schoeberl, J. Sparsø","doi":"10.1109/NORCHIP.2015.7364392","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364392","url":null,"abstract":"This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors in the platform. Our design takes a different approach and connects the hardware accelerators to the network-on-chip in the same way as processor cores. Each processor that uses a hardware accelerator is assigned a virtual channel for sending instructions to the hardware accelerator and a virtual channel for receiving results. This allows a stateless and possibly pipelined hardware accelerator to be shared in an interleaved fashion without any form of reservation, and this opens for interesting area-performance trade-offs. The design is developed with a focus on time-predictability, area-efficiency, and FPGA implementation. The design evaluation is carried out using the open source T-CREST multi-core platform implemented on an Altera Cyclone IV FPGA. The size of the proposed design, including a floating-point accelerator, is about two-thirds of a processor.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124664007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A noise coupled ΣΔ architecture using a Non Uniform Quantizer 使用非均匀量化器的噪声耦合ΣΔ架构
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364400
J. Torreño, S. Patón, Laura Conesa-Peraleja, L. Hernández, Dietmar Straeussnigg
{"title":"A noise coupled ΣΔ architecture using a Non Uniform Quantizer","authors":"J. Torreño, S. Patón, Laura Conesa-Peraleja, L. Hernández, Dietmar Straeussnigg","doi":"10.1109/NORCHIP.2015.7364400","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364400","url":null,"abstract":"A low power Discrete Time Sigma Delta modulator (DT SDM) for sensor applications is described in this paper. A third order noise shaping is reached with a second order loop filter due to the use of a noise coupling technique at the input of the quantizer. Using a Non Uniform Quantizer (NUQ) the hardware complexity is reduced. This architecture is suitable for high dynamic range sensor applications with some compression. Conventional mismatch shaping techniques can still be used to enhance linearity if a segmented DAC is used. At low amplitudes the NUQ is linearized by the noise coupling loop. A simulation example is presented, achieving a dynamic range of 103dB and a peak SNDR of 93dB over 25KHz bandwidth, and using a 1.6MHz clock.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116009331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The low delay low-pass FIR digital differentiators having flat passband and equiripple stopband 具有平通带和等纹阻带的低延迟低通FIR数字微分器
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364411
Takashi Yoshida, N. Aikawa
{"title":"The low delay low-pass FIR digital differentiators having flat passband and equiripple stopband","authors":"Takashi Yoshida, N. Aikawa","doi":"10.1109/NORCHIP.2015.7364411","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364411","url":null,"abstract":"The low-pass maximally flat FIR digital differentiator (low-pass MFDD) provides high accurate differentiation around the frequency ω = 0, while it reduces noises in the high frequency. Recently, authors proposed the low delay low-pass MFDD, but it can not get the steep cutoff characteristic. This paper proposes a design method of the low delay low-pass FIR digital differentiators having the flat passband and the equiripple stopband. The proposed transfer function is consist of the passband function and the stopband function. The passband function realizes the high accurate differentiation and the desired delay at ω = 0. The stopband function provides arbitrary roots in the stopband. Those roots are updated to be the optimal ones by using Remez algorithm iteratively.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116368211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A NAND gate based standard cell VCO for use in synthesizable ADCs 用于可合成adc的基于NAND门的标准单元压控振荡器
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364398
Vishnu Unnikrishnan, M. Vesterbacka
{"title":"A NAND gate based standard cell VCO for use in synthesizable ADCs","authors":"Vishnu Unnikrishnan, M. Vesterbacka","doi":"10.1109/NORCHIP.2015.7364398","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364398","url":null,"abstract":"Synthesizable all-digital ADCs lead to reduced design cost and design time as well as to low cross-technology porting costs. VCO-based ADC is an attractive candidate for the synthesis of ADCs using standard cells. However, a VCO, which is controlled by an analog input signal, is difficult to implement using standard digital circuits. Supply controlled ring oscillators using static CMOS inverters are used in prior works. In this work, an alternative VCO built using NAND gates is proposed for use in synthesizable converters. The circuit is demonstrated by employing it in an ADC synthesized from an HDL description. Transistor level simulation of the resulting netlist using the Spectre simulator shows that a performance of 10 bit ENOB over a 10 MHz bandwidth can be achieved after digital correction, using the proposed VCO.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114947521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of a highly linear, low noise, broad band up-converter for cognitive radio applications 一种用于认知无线电应用的高线性、低噪声、宽带上变频器的设计
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364393
G. Varga, A. Ashok, I. Subbiah, M. Schrey, S. Heinen
{"title":"Design of a highly linear, low noise, broad band up-converter for cognitive radio applications","authors":"G. Varga, A. Ashok, I. Subbiah, M. Schrey, S. Heinen","doi":"10.1109/NORCHIP.2015.7364393","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364393","url":null,"abstract":"In this paper steps for the systematic design and simulation of an integrated up-conversion mixer in a 130 nm CMOS technology are carried out. It is designed to up-convert the broad TV White Space band from 470 MHz-790 MHz to a variable intermediate frequency of 1.6 GHz-2.6 GHz to enable Cognitive Radio of commercial LTE or WLAN devices in the TV White Space. The specialty of the mixer is easing the tradeoff between high linearity and low noise at for mobile use realistic power consumption. Starting from overall requirements, system considerations are shown to find the best fitting architecture. The building circuits are specified, designed and verified. The overall performance is simulated including the most significant external parasitic effects.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134009016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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