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An ultra wide-band adaptive frequency divider for mm-wave PLL applications 一种用于毫米波锁相环应用的超宽带自适应分频器
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364366
P. Athanasiadis, L. Mountrichas, S. Siskos
{"title":"An ultra wide-band adaptive frequency divider for mm-wave PLL applications","authors":"P. Athanasiadis, L. Mountrichas, S. Siskos","doi":"10.1109/NORCHIP.2015.7364366","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364366","url":null,"abstract":"Trying to achieve the maximum frequency range at which a PLL for mm-wave applications operates, an ultra wide-band frequency divider was implemented exploiting the load modulation of existing dynamic latch based frequency dividers topology. The result was an adaptive divider with input frequency range from 28GHz to 80GHz without external trimming. The divider was implemented on TSMC CMOS 65nm technology at 1V power supply, with 11.5mW maximum power dissipation.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122975915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation 具有低调谐电压灵敏度和温度补偿的3.6 GHz CMOS环形振荡器
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364354
Hasene Gulperi Ozsema, T. Demirci, Y. Leblebici
{"title":"3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation","authors":"Hasene Gulperi Ozsema, T. Demirci, Y. Leblebici","doi":"10.1109/NORCHIP.2015.7364354","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364354","url":null,"abstract":"In this paper we present the design of a temperature compensated low-tune-voltage-sensitive CMOS ring oscillator in 40nm standard CMOS technology. The oscillator has an overall frequency range from 3.1 GHz to 3.6 GHz. The effect of temperature variations on the frequency span has been tuned out by an IPTAT (inversely proportional to absolute temperature) current reference. In this work, using a coarse-fine tuning mechanism lowers the tune range sensitivity of the oscillator, which is usually represented as KVCO. The achieved KVCO is around 490 MHz/V with 400 mV tune voltage sweep. The area and the power consumption of the ring oscillator are 0.0056 mm2 and 0.9 mW.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"28 3-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116714480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low power, highly stable and wideband LNA for GNSS applications in SiGe technology 低功耗，高稳定和宽带LNA，用于SiGe技术的GNSS应用
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-26 DOI: 10.1109/NORCHIP.2015.7364395
Navneeta Deo, J. Wernehag, J. Thelberg
{"title":"Low power, highly stable and wideband LNA for GNSS applications in SiGe technology","authors":"Navneeta Deo, J. Wernehag, J. Thelberg","doi":"10.1109/NORCHIP.2015.7364395","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364395","url":null,"abstract":"A low power wideband low noise amplifier (LNA) was designed and implemented in SiGe HBT technology. The measured noise figure is less than or equal to 1 dB in almost the entire L-band. The gain in the L-band is above 13 dB with a gain variation of 4 dB. Hence, it's useful for present as well as future GNSS applications. A single supply of +5V is used. The active current consumption is 5 mA for a collector to emitter voltage of 3V. The stability of the design was tested using various simulations prior to actual implementation which greatly helped in preventing oscillations in the circuit. It is found to be unconditionally stable in the frequency range of 40 MHz to 40 GHz. The design consists of simple matching and DC bias networks making it small in size and cost-effective.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116624204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Formal analysis of macro synchronous micro asychronous pipeline for hardware Trojan detection 宏同步微异步管道硬件木马检测的形式化分析
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364384
F. Lodhi, S. R. Hasan, O. Hasan, F. Awwad
{"title":"Formal analysis of macro synchronous micro asychronous pipeline for hardware Trojan detection","authors":"F. Lodhi, S. R. Hasan, O. Hasan, F. Awwad","doi":"10.1109/NORCHIP.2015.7364384","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364384","url":null,"abstract":"Globalization trends in integrated circuit (IC) design using deep submicron (DSM) technologies are leading to increased vulnerability of IC against malicious intrusions. These malicious intrusions are referred to hardware Trojans. One way to address this threat is to utilize unique electrical signatures of ICs, and any deviation from this signature helps in detecting the potential attack paths. Recently we proposed hybrid macro synchronous micro asynchronous (MSMA) pipeline technique while utilizing, non-conventional, asynchronous circuits to generate timing signature. However, traditionally generating these timing signatures with environmental uncertainties require extensive simulations. It is known to the engineering community that computer simulations have its limitations due to the associated heavy computational requirements. In this paper, as a more accurate alternative, we propose a framework to detect the vulnerable paths in the MSMA pipeline for hardware Trojan detection using formal verification methods. In particular, the paper presents a formal model of the MSMA pipeline and its verification results for both functional and timing properties.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123731007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology 全摆幅20ghz分频器，电源电压为1v，采用FD-SOI 28nm技术
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364385
Hasene Gulperi Ozsema, Duygu Kostak, T. Demirci, Y. Leblebici
{"title":"Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology","authors":"Hasene Gulperi Ozsema, Duygu Kostak, T. Demirci, Y. Leblebici","doi":"10.1109/NORCHIP.2015.7364385","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364385","url":null,"abstract":"In this paper we present the design of a programmable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divide-by-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and 254. The forward-body-bias property of the process and the differential-cascode voltage-switch-logic (DCVSL) family are used to achieve high operation speed. The proposed circuit achieves a maximum operating frequency of 20 GHz at 1 V supply voltage. And the area and the power consumption of the programmable divider are 1815 μm2 and 4.35 mW, respectively.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130183103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wide band edge-coupled impedance matching network with quarter wavelength measurement circuit 带四分之一波长测量电路的宽带边缘耦合阻抗匹配网络
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364417
H. Amin, B. Yarman
{"title":"Wide band edge-coupled impedance matching network with quarter wavelength measurement circuit","authors":"H. Amin, B. Yarman","doi":"10.1109/NORCHIP.2015.7364417","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364417","url":null,"abstract":"This paper presents design and measurement of a wide band-pass edge-coupled resistive impedance matching network, matching 12.5 ohm to 50 ohm having bandwidth of 2.4Ghz over the center frequency of 4Ghz. Edge-coupled filters are mostly used in wideband applications. This paper investigates design and implementation of a wide band edge coupled impedance matching networks. Impedance matching is accomplished using a coupled line filter with quarter wavelength terminations. Also, for measurement purposes, a test circuit is designed by cascaded quarter wavelength transmission line technique. The test circuit, is realized on 1mm FR4 substrate and measured by Power Network Analyzer (PNA). The design procedures and of both band-pass impedance matching network and test circuit are studied in details.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133615885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Self-biasing high-voltage driver based on standard CMOS with an adapted level shifter for a wide range of supply voltages 基于标准CMOS的自偏置高压驱动器，具有适应宽范围电源电压的电平移位器
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364405
Sara Pashmineh, D. Killat
{"title":"Self-biasing high-voltage driver based on standard CMOS with an adapted level shifter for a wide range of supply voltages","authors":"Sara Pashmineh, D. Killat","doi":"10.1109/NORCHIP.2015.7364405","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364405","url":null,"abstract":"This paper presents the design of a high-voltage driver based on stacked standard low-voltage CMOS with an adapted level shifter. Both circuits are designed in 65-nm TSMC technology with a nominal voltage of 2.5 V without any passive elements. The control voltages to regulate the stacked transistors of the HV-driver are achieved by proposing cascode self-biasing method, therefore no reference voltages are required. The driver and the level shifter are optimized for arbitrary supply voltages from 3.5 V to 7.5 V. This range is extended by 66.7% when compared against common drivers and level shifters being suitable for a supply voltage range of 2.4 V between 5.1 V and 7.5 V. The circuit is stable for temperatures between -45 °C and 125 °C , and has no overvoltage between the terminals of each transistor.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129458008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters SAR和ΔΣ模数转换器的基本功率限制
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364387
S. Brenna, Luca Bettini, Andrea Bonetti, A. Bonfanti, A. Lacaita
{"title":"Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters","authors":"S. Brenna, Luca Bettini, Andrea Bonetti, A. Bonfanti, A. Lacaita","doi":"10.1109/NORCHIP.2015.7364387","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364387","url":null,"abstract":"This work aims at estimating and comparing the power limits of ΔΣ and charge-redistribution successive-approximation register (CR-SAR) analog-to-digital converters (ADCs), in order to identify which topology is the most power-efficient for a target resolution. A power consumption model for mismatch-limited SAR ADCs and for discrete-time (DT) ΔΣ modulators is presented and validated against experimental data. SAR ADCs are found to be the best choice for low-to-medium resolutions, up to roughly 80 dB of dynamic range (DR). At high resolutions, on the other hand, ΔΣ modulators become more power-efficient. This is due to the intrinsic robustness of the ΔΣ modulation principle against circuit imperfections and non-idealities. Furthermore, a comparison of the area occupation of such topologies reveals that, at high resolutions and for a given dynamic range, ΔΣ ADCs result more area-efficient as well.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130646531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new current stimulator architecture for visual cortex stimulation 一种新的视觉皮层刺激器结构
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364399
Dmitry Osipov, S. Paul, S. Strokov, A. Kreiter
{"title":"A new current stimulator architecture for visual cortex stimulation","authors":"Dmitry Osipov, S. Paul, S. Strokov, A. Kreiter","doi":"10.1109/NORCHIP.2015.7364399","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364399","url":null,"abstract":"In this paper a new switched reference stimulator architecture for the visual cortex stimulation is presented. Compared with the present alternatives the architecture allows to relax twice requirements of the stimulator output voltage tolerance and to simplify the design of high voltage (HV) switches. The stimulator functionality was proven by fabrication with AMS HV 0.35 μm CMOS technology and the measurement of test chip. The measurement results show the possibility to drive currents from -10 mA up to 10 mA into the tissue, while the electrode-tissue interface resistance is up to 8 kΩ with the effectively high-voltage output compliance of up to 180 V. Wherein the need for HV VDD voltage is limited to 90 V.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115406796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Digital background calibration in continuous-time delta-sigma analog to digital converters 连续时间δ - σ模拟到数字转换器的数字背景校准
2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-10-01 DOI: 10.1109/NORCHIP.2015.7364377
Siyu Tan, Yun Miao, Mattias Palm, J. Rodrigues, P. Andreani
{"title":"Digital background calibration in continuous-time delta-sigma analog to digital converters","authors":"Siyu Tan, Yun Miao, Mattias Palm, J. Rodrigues, P. Andreani","doi":"10.1109/NORCHIP.2015.7364377","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364377","url":null,"abstract":"This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65nm CMOS process. The maximum simulated signal-to-noise and distortion ratio (SNDR) is 67.1dB within 9MHz bandwidth.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131533951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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