2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)最新文献_第2页

A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise 具有带内相位噪声的65nm CMOS分数n数字锁相环

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364356

Ahmed Mahmoud, P. Andreani, P. Lu

引用次数: 1

Fixed pattern noise correction for wide dynamic range CMOS image sensor with Reinhard tone mapping operator 基于Reinhard色调映射算子的宽动态范围CMOS图像传感器固定模式噪声校正

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364383

Waqas Mughal, B. Choubey

{"title":"Fixed pattern noise correction for wide dynamic range CMOS image sensor with Reinhard tone mapping operator","authors":"Waqas Mughal, B. Choubey","doi":"10.1109/NORCHIP.2015.7364383","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364383","url":null,"abstract":"This paper presents an investigation and a correction technique for fixed pattern noise in wide dynamic range image sensor with on the focal plane Reinhard tone mapping. The Human eye is capable of capturing images over a wide dynamic range of illumination; however, typical CMOS image sensors have limited ability to capture dynamic range available in nature. Even when wide dynamic range images are captured, they need to be displayed on conventional media with limited ability to display WDR scenes. Hence, the image has algorithmically transformed by mathematical operators called tone mapping operators to fit the limited dynamic range. In this paper, we report our research on a pixel, which captures a scene with inbuilt tone mapping operator, particularly, the Reinhard photographic mapping operator, which is a monotonically increasing function. However, the inherent Fixed pattern noise(FPN) limits the performance of image sensors. This is mainly due to the variations between the responses of individual pixels within an array of pixels. A simple procedure has been adapted to reduce FPN in which parametric response of the pixel is used, with FPN modeled as variations in the individual parameters. The parameters of each individual pixel are measured, recorded and then used to correct their response.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"70 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134092599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Highly linear and reliable low band class-O RF power amplifier in 130 nm CMOS technology for 4G LTE applications 高线性和可靠的低频段o类射频功率放大器，采用130纳米CMOS技术，用于4G LTE应用

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364389

Muhammad Abdullah Khan, A. Aref, M. Wei, R. Negra

{"title":"Highly linear and reliable low band class-O RF power amplifier in 130 nm CMOS technology for 4G LTE applications","authors":"Muhammad Abdullah Khan, A. Aref, M. Wei, R. Negra","doi":"10.1109/NORCHIP.2015.7364389","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364389","url":null,"abstract":"This paper presents a highly linear low-band 706MHz LTE compatible class-O RF power amplifier in 130nm CMOS technology for handheld wireless applications. Class-O topology uses a combination of common-source and common-drain amplifiers working in parallel with high linearity without the need for digital predistortion(DPD). With continuous wave measurements, 1-dB compression point (P1dB) of 30.6dBm and peak power added efficiency (PAE) of 45.2% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an ACPR less than -30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common-source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst VSWR conditions.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm 超低功耗/高速9位加法器设计:从130nm-LP到UTBB FD-SOI-28nm技术的分析与比较

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364365

H. Attarzadeh, S. Aunet, T. Ytterdal

{"title":"An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm","authors":"H. Attarzadeh, S. Aunet, T. Ytterdal","doi":"10.1109/NORCHIP.2015.7364365","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364365","url":null,"abstract":"A sub-threshold 9-bit adder based on a minority-3 based full adder is designed and analyzed versus technology. A power-delay design space exploration is presented in multiple technology nodes. The performances are demonstrated and compared on spanning technology nodes of 130nm-LP, 65nm-LP-BULK, 28nm-LP-high-k-bulk, 28nm Ultra-Thin-Body-and-BOX (UTFF) FDSOI. An extensive body biasing was then applied to the UTBB FDSOI 28nm technology to adapt the circuit to the target operating frequency of 65MHz. The extensive body biasing exploits the feature provided by the Ultra-Thin-Body-and-BOX Fully Depleted SOI (UTBB FDSOI) technology, which allows a bias range of -300mV ~3V . The design was implemented in physical level, and all the results account for the layout parasitics. A minimum energy point of 1.03f J/(bit.cycle) is achieved in the 28nm-UTFF-FDSOI, at the 0.24V supply with the 1.8MHz operating speed. For the target frequency of 65MHz and a 9-bit adder, a total minimum energy operation of 11f J percycle for a supply voltage of 0.309V and a body voltage of 1.35V is achieved.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"315 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133287189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A comparison of serial interfaces on energy critical systems 能量关键系统串行接口的比较

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364373

Tharald Solheim, Marius Grannaes

引用次数: 7

Ultra low power on-chip hybrid start-up for wireless sensor networks 超低功耗片上混合启动无线传感器网络

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364415

N. Vamsi, A. Gupta, A. Dutta, S. Singh

引用次数: 2

On-chip spatial filter for subretinal implants 用于视网膜下植入物的片上空间滤波器

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364401

V. Rieger, Henning Schütz, Stefan Gambach, A. Rothermel

引用次数: 2

Process tolerant highly linear mixer output stage with feedforward linearity improvement method for a high-IF converter 高中频变换器的过程容忍高线性混频器输出级及前馈线性度改进方法

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364403

A. Ashok, G. Varga, I. Subbiah, M. Schrey, S. Heinen

{"title":"Process tolerant highly linear mixer output stage with feedforward linearity improvement method for a high-IF converter","authors":"A. Ashok, G. Varga, I. Subbiah, M. Schrey, S. Heinen","doi":"10.1109/NORCHIP.2015.7364403","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364403","url":null,"abstract":"A highly linear output stage for passive mixers in mixer-first front-ends is presented. Passive nature and mixer-first can provide high linearity for a transmit chain front-end and the linearity is generally limited by the mixer output stage and the succeeding stages. The output amplifier design presented in this paper utilizes feedforward cancellation using an auxiliary transistor to cancel the Inter-Modulation Distortion (IMD3) products to improve the linearity. With the addition of this feedforward technique a linearity improvement of 8 dB can be obtained by optimum biasing. In order to reduce the dependence of linearity under process variations, constant-gm biasing scheme is used and bias points are selected such a way that the resulting variation from process is still within the specification. The third order intermodulation point (IIP3) of such a linearized stage is 22dBm for a frequency of 500 MHz. The total current consumption and gain are 4mA and 10 dBV respectively. The design is performed in CMOS130 technology with 3.3V power supply.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127107577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI 28nm FDSOI中亚阈值应用的触发器架构比较分析

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364372

E. Låte, A. Vatanjou, T. Ytterdal, S. Aunet

引用次数: 1

A design platform for flexible programmable DSP for automotive sensor conditioning 基于柔性可编程DSP的汽车传感器调理设计平台

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364361

A. Sisto, Luca Pilato, R. Serventi, L. Fanucci

引用次数: 2