2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)最新文献_第3页

A compact 0.3–10 GHz broadband stacked amplifier in 65nm standard CMOS 一个紧凑的0.3-10 GHz宽带堆叠放大器在65nm标准CMOS

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364360

M. Tarar, M. Wei, R. Negra

引用次数: 1

Systematic frequency planning for a high SFDR digital-IF RF-DAC-based transmitter 高SFDR数字中频rf - dac发射机的系统频率规划

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364409

Oner Hanay, Erkan Bayram, M. Elsayed, R. Negra

引用次数: 3

Design and evaluation of correlation accelerator in IEEE-802.11a/g receiver using a template-based Coarse-Grained Reconfigurable Array 基于模板的粗粒度可重构阵列的IEEE-802.11a/g接收机相关加速器设计与评价

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364374

Sajjad Nouri, Waqar Hussain, J. Nurmi

引用次数: 4

Single chip wireless condition monitoring of power semiconductor modules 功率半导体模块的单芯片无线状态监测

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364407

J. Nilsson, J. Borg, J. Johansson

引用次数: 5

A fully synthesized all-digital VCO-based analog-to-digital converter 全合成全数字基于vco的模数转换器

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364386

Vishnu Unnikrishnan, Srinivasa Rao Pathapati, M. Vesterbacka

引用次数: 4

A 10-bit reference free current mode SAR ADC with 58.4 dB SFDR at 50 MS/s in 90 nm CMOS 一个10位参考自由电流模式SAR ADC，在90 nm CMOS中具有58.4 dB的SFDR, 50 MS/s

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364355

Abdelrahman Elkafrawy, J. Anders, M. Ortmanns

引用次数: 4

Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator 利用变长环振荡器跟踪脉宽控制锁相环的PVT变化

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364412

Takashi Toi, T. Nakura, T. Iizuka, K. Asada

引用次数: 2

Design, implementation and analysis of a run-time configurable Memory Management Unit on FPGA 基于FPGA的运行时可配置内存管理单元的设计、实现与分析

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364375

Farid Shamani, Vida Fakour Sevom, J. Nurmi, T. Ahonen

{"title":"Design, implementation and analysis of a run-time configurable Memory Management Unit on FPGA","authors":"Farid Shamani, Vida Fakour Sevom, J. Nurmi, T. Ahonen","doi":"10.1109/NORCHIP.2015.7364375","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364375","url":null,"abstract":"In this paper, we describe the design of a configurable Memory Management Unit (MMU) and its prototype implementation on a Field Programmable Gate Array (FPGA). We present analytical results of scaling the size of the second level software-managed Unified Translation Lookaside Buffer (UTLB) in terms of effect on the overall hit rate. Three design-time configurations with 16, 32, and 64 entries were used for this study. Critical path analysis of the logical design running on Altera Stratix-V FPGA is presented together with a description of optimization techniques employed in order to improve static timing performance. These optimization techniques assist in reaching 22.75% speed-up compared to non-optimized design. Moreover, maximum operating frequencies of 265, 225 and 200 MHz were achieved for UTLB sizes of 16, 32, and 64 entries, respectively. We quote worst case energy consumption figures with random input stimuli together with FPGA resource utilization characteristics for the above mentioned configurations. For resource-constrained or speed-critical hardware designs the 32-entry UTLB configuration provides a decent trade-off while the 16-entry configuration poses unsatisfactory performance. However, our target operating frequency of 200 MHz was eventually reached also for the 64-entry UTLB and hence it is our preferred option for most instantiations.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127622014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Design of a hybrid multicore platform for high performance reconfigurable computing 高性能可重构计算混合多核平台设计

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364376

Waqar Hussain, H. Hoffmann, T. Ahonen, J. Nurmi

{"title":"Design of a hybrid multicore platform for high performance reconfigurable computing","authors":"Waqar Hussain, H. Hoffmann, T. Ahonen, J. Nurmi","doi":"10.1109/NORCHIP.2015.7364376","DOIUrl":"https://doi.org/10.1109/NORCHIP.2015.7364376","url":null,"abstract":"This paper presents a loosely-coupled, hybrid architecture of homogeneous and heterogeneous cores integrated together over a Network-on-Chip (NoC). The architecture efficiently utilizes the NoC bandwidth by keeping a balance between the instantiated number of computational and communication nodes. Furthermore, the architecture also provides a mixed flavor of homogeneous general-purpose processing and heterogeneous reconfigurable computing. Prior approaches have mostly considered homogeneous and heterogeneous platforms as two different design paradigms despite both show domain-specific performance advantages over each other. In this context, the proposed architecture is designed for nine NoC nodes, arranged in a topology of three rows and three columns. The middle row contains three homogeneous Reduced Instruction Set Computer (RISC) cores and rest of the nodes are integrated with Coarse-Grain Reconfigurable Arrays (CGRAs) of application-specific sizes. The overall architecture is template-based which can be crafted to application's performance requirements. The NoC allows loose coupling, so all the cores can mutually exchange the data as well as enable independent and simultaneous execution. Contrarily, the user can program the middle layer of RISC cores for specific data/control dependencies among all the cores. The system mitigates power dissipation as the CGRAs are custom tailored for heterogeneous computing. The platform is evaluated for a proof-of-concept test comprising of massively-parallel signal processing algorithms. Synthesis results from a Field Programmable Gate Array device are used to establish comparisons and evaluation against some of the existing state-of-the-art multicore platforms in terms of multiple performance metrics.","PeriodicalId":428994,"journal":{"name":"2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122644500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Inductorless and cross-coupled wideband LNA with high linearity 具有高线性度的无电感交叉耦合宽带LNA

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) Pub Date : 2015-12-28 DOI: 10.1109/NORCHIP.2015.7364391

David Bierbuesse, P. Bousseaud, R. Negra

引用次数: 3