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Proceedings of the Workshop on Low Temperature Semiconductor Electronics,最新文献

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Semiconductor devices and superconducting interconnections at 77 K: super-semi or semi-super 77k下的半导体器件和超导互连:超级半超级或半超级
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50173
S. Tewksbury, L. Hornak, M. Hatamian
{"title":"Semiconductor devices and superconducting interconnections at 77 K: super-semi or semi-super","authors":"S. Tewksbury, L. Hornak, M. Hatamian","doi":"10.1109/LTSE.1989.50173","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50173","url":null,"abstract":"It is noted that, with semiconductor logic at 77 K providing an optimized, local active device behavior for logical operations, high-T/sub c/ superconducting transmission lines and Josephson tunnel junction drivers/receivers can provide a similarly optimized communications environment at 77 K. This combination of low-temperature active electronic devices and high-temperature superconducting interconnections is considered in the present work. The potential performance of transmission lines fabricated from thin-film, high-T/sub c/ superconductors is examined, and several practical issues degrading the potential performance of such interconnections are considered. Attention is given to issues connected with surface impedance, flux motion induced resistance, critical current density, thin film substrates, multilayer interconnections, high-quality surfaces, tunnel junction devices, large-area substrates, and reliability.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130338105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A numerical simulation of the transient drain current in a MOST at cryogenic temperatures 低温条件下MOST瞬态漏极电流的数值模拟
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50183
M. Grupen, C. Viswanathan
{"title":"A numerical simulation of the transient drain current in a MOST at cryogenic temperatures","authors":"M. Grupen, C. Viswanathan","doi":"10.1109/LTSE.1989.50183","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50183","url":null,"abstract":"The authors present a numerical technique to model the transient in the drain current when the MOS transistor is suddenly switched on at low temperatures. The technique is similar to those used in steady-state simulations of MOS devices. However, the physical principles that apply to a transient simulation are very different from those of the steady-state model. Consequently, new boundary conditions and new physical relationships that predict semiconductor charge densities are derived. The transient predicted by the simulation is compared to the measured data, verifying the principles upon which the simulation is based. The simulation shows that the field-enhanced ionization of dopant atoms can be accurately modeled using Shockley-Read-Hall statistics and Poole-Frenkel expressions. The hole capture cross-section for the acceptor atoms was about 2*10/sup -12/ cm/sup 2/.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117038169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Characterization and modeling of BiCMOS logic for low temperature operation 低温运行BiCMOS逻辑的表征与建模
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50170
P. Heedley, R. Jaeger
{"title":"Characterization and modeling of BiCMOS logic for low temperature operation","authors":"P. Heedley, R. Jaeger","doi":"10.1109/LTSE.1989.50170","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50170","url":null,"abstract":"The results of using a closed-form analytic model for the transient response of a BiCMOS inverter to determine bipolar device requirements for acceptable BiCMOS operation at low temperatures are presented. Measurements of bipolar device parameters versus temperature for bipolar devices fabricated in a BiCMOS process are presented and combined with model predictions of gate delay dependence on these key parameters to predict how gate delay varies with temperature. The predictions are compared to BiCMOS ring oscillator measurements over the temperature range of 77 K to 350 K. It is shown that, although BiCMOS gate delay does not substantially increase until far below room temperature, operation of present BiCMOS gates at low temperatures does not yield speed advantages similar to those seen in CMOS gates. However, since this is due to poor bipolar device performance at low temperatures, it is concluded that careful optimization of critical device parameters, such as B/sub f/, for low-temperature operation holds significant promise.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"2019 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114577118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Refrigeration for low temperature (77 K) electronics 低温(77 K)电子制冷
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50187
R. Longsworth
{"title":"Refrigeration for low temperature (77 K) electronics","authors":"R. Longsworth","doi":"10.1109/LTSE.1989.50187","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50187","url":null,"abstract":"The authors discuss the present state of the art and options that are being pursued to develop cryogenic coolers that will help make cryogenic electronic systems competitive. The discussion focuses on commercial systems operating in the 77-K temperature region with cooling requirements of about 10 to 1000 W. It is noted that the present perception is that the initial plus operating cost is too high and the life/service interval too short for Gifford McMahon refrigerators to make cryogenic electronic devices competitive with room-temperature devices. Stirling refrigerators offer the promise of lower costs and longer life; it will, however, take a number of years to realize the promise. High reliability in the refrigerator will make it possible to use the lower cost method of direct mounting the electronic device to the refrigerator.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115016297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low temperature SER and noise in a high speed DRAM 高速DRAM中的低温SER和噪声
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50171
W. Henkels, N. Lu, W. Hwang, T. Rajeevakumar, R. Franch, K. Jenkins, T. Bucelot, D. Heidel, M. Immediato
{"title":"Low temperature SER and noise in a high speed DRAM","authors":"W. Henkels, N. Lu, W. Hwang, T. Rajeevakumar, R. Franch, K. Jenkins, T. Bucelot, D. Heidel, M. Immediato","doi":"10.1109/LTSE.1989.50171","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50171","url":null,"abstract":"The soft error rate (SER) and power bus noise were measured for a high-speed 512 kb CMOS DRAM (dynamic random access memory) operated at liquid-nitrogen temperatures. The SER decreased by about 3-20 times, depending upon cycle time and data type, and the power bus noise increased, but only modestly, at low temperature. These results show that the noise and SER do not preclude high-speed cryogenic DRAM operation. Compensation of increased inductive noise by decreased resistive noise is found to be a significant advantage in obtaining speed improvement by temperature reduction, rather than by room-temperature circuit and device techniques.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117103534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Substrate bias effects on short channel length and narrow channel width PMOS devices at cryogenic temperatures 低温条件下衬底偏压对短通道长度和窄通道宽度PMOS器件的影响
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50181
M. Deen, J. Wang, Z.X. Yan, Z. Zuo
{"title":"Substrate bias effects on short channel length and narrow channel width PMOS devices at cryogenic temperatures","authors":"M. Deen, J. Wang, Z.X. Yan, Z. Zuo","doi":"10.1109/LTSE.1989.50181","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50181","url":null,"abstract":"The effects of substrate biasing on the characteristics of PMOS devices with varying channel lengths and widths were studied as a function of temperature from 300 K to 77 K. Results on the low field intrinsic mobility, the mobility surface and substrate bias degradation constants, and the effective low field mobility are discussed. The variation of the peak substrate current normalized to the drain current and of drain-induced-barrier-lowering with substrate bias for both groups of devices is also presented and discussed.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125197923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impact of floating the well contact on the low temperature kink in n-channel CMOS transistors 浮动井触点对n沟道CMOS晶体管低温扭结的影响
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50196
K.L. Kasley, G. Oleszek, R. Anderson
{"title":"Impact of floating the well contact on the low temperature kink in n-channel CMOS transistors","authors":"K.L. Kasley, G. Oleszek, R. Anderson","doi":"10.1109/LTSE.1989.50196","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50196","url":null,"abstract":"The effect of electrically floating the well on the low-temperature kink in n-channel CMOS transistors was investigated experimentally. I/sub d/-V/sub d/ (drain current-drain voltage) curves at 13 K with the well grounded and with the well floating were obtained. The low-temperature kink in the I/sub d/-V/sub d/ characteristics of n-channel CMOS transistors was found to be affected by the contact of the well. When the well contact is floated, only the first I/sub d/-V/sub d/ trace displays a kink and hysteresis. Subsequent curves show little, if any, kink, but are consistent with the after-kink drain currents measured with the well contact grounded.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130948682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel method for characterizing degradation of MOSFETs caused by hot-carriers 一种表征热载流子引起的mosfet退化的新方法
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50194
A. Acovic, M. Dutoit, M. Ilegems
{"title":"A novel method for characterizing degradation of MOSFETs caused by hot-carriers","authors":"A. Acovic, M. Dutoit, M. Ilegems","doi":"10.1109/LTSE.1989.50194","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50194","url":null,"abstract":"A novel method for characterizing HC (hot carrier) degradation in MOSFETs, based on the measurement of the field-induced drain-substrate tunnel diode at 77 K, is proposed. This method is applied to MOSFETs stressed at 300 K and 77 K. The measurements demonstrate the creation of interface states directly above the n/sup +/ zone in NMOSFETs and trapped negative charge in its vicinity. In PMOSFETs damage occurs closer to the channel. It is also shown that the greater degradation of the electrical characteristics of NMOSFETs during HC stress at low temperature is not solely due to the increased effective damage (interface states or trapped charge), but is also due to the increased effects of a given damage.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129234678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low temperature MOS device modeling 低温MOS器件建模
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50184
S. Selberherr, E. Langer
{"title":"Low temperature MOS device modeling","authors":"S. Selberherr, E. Langer","doi":"10.1109/LTSE.1989.50184","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50184","url":null,"abstract":"The state of the art in self-consistent numerical low-temperature MOS modeling is reviewed. The physical assumptions required to describe carrier transport at liquid-nitrogen temperature are discussed. Particular emphasis is put on the models for space charge (impurity freeze-out), carrier mobility (temperature dependence of scattering mechanisms at a semiconductor-insulator interface), and carrier generation-recombination (impact ionization). The differences with regard to the numerical methods required for the solution of low-temperature models compared to room-temperature models are explained. Typical results obtained with the simulator MINIMOS 4 are presented.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127893796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Investigation of MCT behaviour at low temperatures 低温下MCT行为的研究
Proceedings of the Workshop on Low Temperature Semiconductor Electronics, Pub Date : 1989-08-07 DOI: 10.1109/LTSE.1989.50188
C.S. Jezierski, V. Temple
{"title":"Investigation of MCT behaviour at low temperatures","authors":"C.S. Jezierski, V. Temple","doi":"10.1109/LTSE.1989.50188","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50188","url":null,"abstract":"Tests were performed on MOS-controlled thyristors (MCTs) operating at temperatures ranging from room temperature (298 K, 25 degrees C) down to liquid-nitrogen temperature (77 K, -196 degrees C). Since this is a preliminary study, the MCTs tested were not specifically designed designed for low-temperature operation. Standard diodes were also tested in this temperature range in order to compare the behavior of such a basically simple device to that of the MCT. V-on and I-on (related to MCT latching current and turn-on design), breakdown voltage, V-forward, and I-off time were measured for various devices under test. It was found that the changes with decreasing temperature of five parameters (V-on, I-on, V-forward, I-off time, and conduction phase angle reduction) can be at least partially compensated by reducing the radiation dose. The rates of change of parameters with temperature are considered; some are fairly linear, while others display abrupt changes at transition regions.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127905200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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