{"title":"The effect of the vertical electric field on freeze-out in MOS-structures","authors":"S. Voges, M. du Plessis","doi":"10.1109/LTSE.1989.50178","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50178","url":null,"abstract":"It is well known that majority carrier freeze-out at cryogenic temperatures does not occur in the channel region of an enhancement-mode MOSFET. However, no adequate explanation for this lack of freeze-out has thus far been presented. The authors examine the effect of the vertical electric field under the gate of the MOSFET on frozen-out carriers in the region and present a new theory to explain the lack of freeze-out in this area in terms of a Zener-type ionization of frozen-out carriers. Theoretical calculations show that it is likely that the ionization of the frozen-out carriers in the depletion region under the gate of a MOS transistor is indeed due to the effect of the vertical electric field under the gate. It is shown theoretically that a steady state of complete ionization within the depletion region is reached at a sufficiently low gate voltage within an acceptable time for this effect to be the cause of the non-freeze-out phenomenon. The theory provides a possible explanation for anomalous device behavior encountered at cryogenic temperatures during initial measurements on depletion-mode MOSFETS as well as pn-junction diodes.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116952782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The extraction of electrical parameters for MOSFETs with applications to low temperature","authors":"J. L. Hill, R. Anderson","doi":"10.1109/LTSE.1989.50182","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50182","url":null,"abstract":"The authors examine six models for predicting triode region MOSFET behavior. The six models are formed from the combination of two channel charge models and three carrier velocity models. The channel charge and velocity descriptions are well documented in the literature, but only four of the models have been compared with experiment. It is shown that all six models predict identical MOSFET characteristics for sufficiently small drain voltages. It is shown that, at temperatures high enough that channel carrier freezeout is negligible, it is acceptable to extract MOSFET parameters from the transfer characteristics using methods derived from the simple square law model without velocity saturation. However, due to channel carrier freezeout onto the minority impurity sites for device bodies which contain both donors and acceptors, these methods are invalid at low temperatures. It is also shown that the hole saturation velocity in the channel increases with decreasing temperature. Between room and liquid-nitrogen temperatures, the increase is about 44%.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"380 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124740734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hot-carrier degradation of LDD n-channel MOSFETs at 77 K","authors":"S. Titcomb, K. T. Paskiet, A.E. Grass","doi":"10.1109/LTSE.1989.50193","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50193","url":null,"abstract":"Hot-carrier degradation in lightly-doped drain (LDD) n-channel MOSFETs stressed at 77 K and 300 K was studied. Both short (L=1.3 mu m) and long (L=50 mu m) channel devices were stressed with both DC and pulsed gate biases. Short channel devices were stressed with a drain voltage of 5 V. The DC gate bias was 2.4 V, and the pulsed gate signal was a 1 MHz square wave of 0 to 5 V. Long channel devices were stressed at a drain voltage of 6 V, with the gate pulsed from -7 to 15 V. Drain characteristics and charge-pumping measurements indicate interface state generation at the drain end of the channel. In addition, hole injection led to trapped holes in the oxide at the drain end of the channel. Electron trapping at trapped hole sites in the oxide was observed in the long channel devices.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130343884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A two-dimensional model for the kink in nMOSTs operating at liquid helium temperatures","authors":"E. Simeon, L. Deferm, C. Claeys","doi":"10.1109/LTSE.1989.50195","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50195","url":null,"abstract":"A model for the kink in MOSTs (MOS transistors) operating at liquid-helium temperatures is presented. It is based on a calculation of the multiplication current as a function of temperature. Subsequently the increase in substrate potential and in drain current is determined, taking account of the current flow through the highly resistive, frozen-out substrate/well. This model makes it possible to explain the temperature and geometry dependence of the kink and can be extended to the case of (cryogenic) SOI (silicon on insulator). With this model it is possible to evaluate and optimize the influence of technological and design parameters for cryogenic applications. It is expected that the well/contact separation plays a crucial role in kink behavior; furthermore, different behavior is expected for n-well technology compared with p-well.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131333534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A numerical study of the temperature dependence of the unity gain frequency of silicon bipolar transistors","authors":"M. Chrzanowska-Jeske, R. Jaeger","doi":"10.1109/LTSE.1989.50177","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50177","url":null,"abstract":"The dependence of the unity gain frequency f/sub T/ of a silicon double-diffused bipolar transistor on temperature and collector current density at 77-300 K is discussed. The f/sub T/ characteristics are generated by the low-temperature bipolar transistor simulator BILOW. Physical explanations of the f/sub T/ plots are given on the basis of simulated distributions of various internal parameters of the bipolar transistor. The temperature dependence of f/sub T/ is found to be strongly influenced by the charge of the minority carriers trapped in the base on the compensated impurity atoms. The electric-field distribution within the base is changed as a result of the additional charge.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121294935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The multistable charge controlled memory effect in SOI-transistors at low temperatures","authors":"M. Tack, M. Gao, C. Claeys, G. Declerck","doi":"10.1109/LTSE.1989.50198","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50198","url":null,"abstract":"The operation of nMOS-transistors, made in SOI material, is investigated at low temperatures. A new phenomenon, the MCCM (multistable charge controlled memory) effect, is observed. Measurements demonstrating this MCCM effect are presented on nMOS transistors made in ZMR-SOI material. A physical model and an analytical model are given. Finally, some very promising applications of the MCCM-effect are highlighted, such as its use as a visible light sensor and as a very dense memory cell, with refresh times on the order of several hours.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"84 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113971964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Operation of GaAs MESFETs at cryogenic temperatures","authors":"C. Liang, H. Wong, N. Cheung","doi":"10.1109/LTSE.1989.50175","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50175","url":null,"abstract":"The device performance of GaAs MESFETs at both quadratic and subthreshold regions was investigated for temperatures ranging from 350 K to 80 K. The measurements at the quadratic region can be described by the empirical hyperbolic tangent model. The device parameters of the model vary with operating temperature. At the subthreshold region, a physical model for the subthreshold drain current of GaAs MESFETs was developed on the basis of an electron-diffusion mechanism. The model was verified by measurements on devices of various gate lengths for different drain and gate bias conditions in the operating temperature range from 350 K to 80 K.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122898301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Fu, S. Liu, M. B. Das, P. Chao, K. Duh, P. Ho, J. Ballingall
{"title":"Comparison of carrier velocity in 0.25 mu m gate-length conventional, pseudomorphic, and lattice-matched modulation-doped FETs at 300 K and 77 K","authors":"S. Fu, S. Liu, M. B. Das, P. Chao, K. Duh, P. Ho, J. Ballingall","doi":"10.1109/LTSE.1989.50174","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50174","url":null,"abstract":"The microwave characterization of 0.25- mu m gate-length MODFETs at 300 and 77 K is reported. Microwave S-parameter measurements of MODFETs from 0.45 to 20 GHz were used to extract their HF equivalent network parameters. After allowing for the parasitic gate and drain-to-gate feedback capacitances, the intrinsic unity-current gain frequency was determined. Using a theoretical model, the effective carrier saturation velocity and average velocity ( nu /sub av/) were obtained for the conventional AlGaAs/GaAs, the pseudomorphic AlGaAs/InGaAs/GaAs, and lattice-matched InAlAs/InGaAs/InAlAs on InP samples at 300 K and 77 K. The extracted values of nu /sub a/ range from 0.82*10/sup 7/ cm/s to 3.84*10/sup 7/ cm/s, respectively, depending on the type of MODFET and operating temperature. These high values of nu /sub av/ indicate that the velocity overshoot effect is present in the devices tested.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121182708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterization and modelling of Si MOSFETs at liquid helium temperature","authors":"F. Balestra, I.M. Hafex, G. Ghibaudo","doi":"10.1109/LTSE.1989.50180","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50180","url":null,"abstract":"A generic analysis of the Si MOSFET operation in the LHT (liquid-helium temperature) range is presented. Analytical models providing current and transconductance transfer characteristics in the linear region and output characteristics in the nonohmic region are proposed. These models rely on a specific mobility law for very low temperature and take into account the effect of source-drain series resistance in both linear and nonlinear regions, which has a drastic influence on the maximum transconductance even for not-too-short channel lengths (L=10 mu m). The influence of carrier velocity saturation at LHT is also considered. A specific parameter extraction method that allows the determination of the main MOSFET parameters is presented. Features of the drain voltage dependence of the mobility at very low longitudinal electric field are pointed out.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"61 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131874270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CMOS operation below freezeout","authors":"S. Broadbent","doi":"10.1109/LTSE.1989.50179","DOIUrl":"https://doi.org/10.1109/LTSE.1989.50179","url":null,"abstract":"A description is given of a cryogenic CMOS process, Rockwell Cryogenic CMOS (RC/sup 2/), for use in readout circuits for impurity band conduction detectors that must operate at a temperature of 12 K or less. The RC/sup 2/ process has been successfully used to implement both analog and digital circuits that operate very well at 10 K. The behavior of RC/sup 2/ FETs in the weak inversion region is discussed. To minimize the power consumption of the large arrays of analog detector readout circuits, the subthreshold region of FET operation is utilized. MOSFETs at these temperatures exhibit the kink effect and have long time constants to reach equilibrium after a large bias change, which must be considered in circuit design. It is concluded that the RC/sup 2/ approach has overcome some of the major obstacles to basic functionality of circuits at temperatures below freezeout and in weak as well as strong inversion.<<ETX>>","PeriodicalId":428125,"journal":{"name":"Proceedings of the Workshop on Low Temperature Semiconductor Electronics,","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134483270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}