2015 International Conference on Electrical Engineering and Informatics (ICEEI)最新文献_第5页

Hardware in-the-loop simulation for visual servoing of fixed wing UAV 固定翼无人机视觉伺服的硬件在环仿真

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352505

Y. A. Prabowo, B. Trilaksono, F. Triputra

{"title":"Hardware in-the-loop simulation for visual servoing of fixed wing UAV","authors":"Y. A. Prabowo, B. Trilaksono, F. Triputra","doi":"10.1109/ICEEI.2015.7352505","DOIUrl":"https://doi.org/10.1109/ICEEI.2015.7352505","url":null,"abstract":"An Image-based fixed wing Unmanned Aerial Vehicle (UAV) has autonomous flight control system which tracks targets to be pursued. This system is more prominent because it is based on visual sight around the aircraft to track the target. Targets will be identified as a feature in the image field captured by camera. By using the position of features in the image, a visual servoing algorithm is implemented to drive servo motors that control the control surfaces such as elevator, aileron, rudder, throttle, pan, and tilt angle on gimbal. Image processing module (Cubieboard2) and visual based autopilot control module (Pixhawk PX4) are used for the UAV on-board systems that become the controller test subject of the hardware in-the-loop simulation (HILS). Native C language program is used for simulating the control plants of UAV and camera attitudes. Whereas, FlightGear is used to visualize camera view and 3D model depend on the calculated UAV and camera attitudes. Then, visualized camera view is projected on screen that is subsequently captured by UAV on-board camera. The HILS results show the responses of the visual based controller to govern the simulated plants of UAV and camera pan-tilt gimbal.","PeriodicalId":426454,"journal":{"name":"2015 International Conference on Electrical Engineering and Informatics (ICEEI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131461411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Comparison of efficiency measurement techniques for electric vehicle traction inverters 电动汽车牵引逆变器效率测量技术比较

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352501

F. Acar, Sadik Ozdemir, H. Akca, U. S. Selamogullari

引用次数: 0

Design and implementation of DCBOTA in Delta-Sigma ADC for communication system 通信系统Delta-Sigma ADC中dbota的设计与实现

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352461

Vincentius Timothy, Aditya Candra, Khafit Mufadli, A. F. Mas'ud, A. H. Salman

引用次数: 1

Usable bibliographic software 可用的书目软件

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352541

Nurul Atiqah binti Zulkharnain, N. S. Ashaari

{"title":"Usable bibliographic software","authors":"Nurul Atiqah binti Zulkharnain, N. S. Ashaari","doi":"10.1109/ICEEI.2015.7352541","DOIUrl":"https://doi.org/10.1109/ICEEI.2015.7352541","url":null,"abstract":"Handling thousands of papers can be a tiring work especially for the researchers. Hence, bibliographic software was created in order to help researchers organise manage, and annotate their references digitally. Vast amounts of research on bibliographic software have been conducted, especially in database or information retrieval but there is a lack of research on interface. A usable interface facilitates researchers in organising reference and making citations. A usable interface should follow usability goals and standards. To ensure the usability of bibliographic software interface, an initial evaluation of the interface is carried out. Bibliographic software evaluation framework is constructed in order to evaluate the bibliographic interface. Therefore, to determine the usability of the interface in this study, a heuristic evaluation was conducted. A Xerox Form was used as the heuristic tools in these evaluations. Only two out of thirteen elements in the Xerox Form are discussed in this paper i.e.- visibility of the system status and match between system and the real world. The evaluation found several problems regarding the interface of the software. This paper ends by suggesting the improvement of bibliographic software interface by using heuristic evaluation.","PeriodicalId":426454,"journal":{"name":"2015 International Conference on Electrical Engineering and Informatics (ICEEI)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126273582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of an FPGA-based sub-module as three-phase spindle motor speed controller for CNC PCB milling machine 基于fpga的数控PCB铣床三相主轴电机调速子模块的研制

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352462

Fiqih Tri Fathulah Rusfa, Farkhad Ihsan Hariadi, A. Sasongko

{"title":"Development of an FPGA-based sub-module as three-phase spindle motor speed controller for CNC PCB milling machine","authors":"Fiqih Tri Fathulah Rusfa, Farkhad Ihsan Hariadi, A. Sasongko","doi":"10.1109/ICEEI.2015.7352462","DOIUrl":"https://doi.org/10.1109/ICEEI.2015.7352462","url":null,"abstract":"Spindle motor (three-phase asynchronous AC motor) is an important part of Computer Numerical Control (CNC) Printed Circuit Board (PCB) milling machine, which plays role to engrave the copper layer based on the PCB pattern design. To perform the engraving processes, it is necessary to adjust the spindle motor speed in accordance with the PCB material used. This paper presents the results of implementing a three-phase spindle-motor speed controller based on Field Programmable Gate Array (FPGA). The control method used is fixed Voltage/Frequency (V/F) with Sinusoidal Pulse Width Modulation (SPWM) technique, so that the maximum torque of the motor can be maintained and the harmonic signals can be minimized. This sub-module consists of two main components, namely FPGA and three-phase inverter, which consists of opto-isolation circuit, logic inverter, MOSFET driver, and three-phase full-bridge inverter circuit. The FPGA unit generates digital SPWM signal as input to the inverter to convert DC voltage into three-phase AC voltage according to the given input frequency. Results show that the sub-module can control the speed in the range of 14000-28000 RPM with the corresponding frequency range of 250-500 Hz. The Sub-module also has constant V/F and Speed/Frequency (ω/F) characteristics. In addition, a ramp speed profile used during acceleration and deceleration has also been successfully implemented to address the problem of low starting torque due to the increase of supply frequency.","PeriodicalId":426454,"journal":{"name":"2015 International Conference on Electrical Engineering and Informatics (ICEEI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123757395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Histogram based color pattern identification of multiclass fruit using feature selection 基于直方图的多类水果颜色模式特征选择识别

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352467

Ema Rachmawati, M. L. Khodra, I. Supriana

{"title":"Histogram based color pattern identification of multiclass fruit using feature selection","authors":"Ema Rachmawati, M. L. Khodra, I. Supriana","doi":"10.1109/ICEEI.2015.7352467","DOIUrl":"https://doi.org/10.1109/ICEEI.2015.7352467","url":null,"abstract":"Color histogram has been widely used in feature extraction to represent color feature of an object in the image. In this paper, we identify which features that give high contribution in classification performance, because not all features are directly correlated with object category. In the case of n-bins color histogram, features were referred to color intensity range of color histogram. On the one hand, we consider fruit classification, where the feature space contains various properties of pixel intensities of RGB (Red-Green-Blue) channel. On selecting feature subset, we consider filter method of feature selection. In the filter method, we successively reduce the size of the feature sets and investigate the changes in the classification results. Specifically, we followed the filtering approach to feature selection: selecting features in a single pass first and then applying a classification algorithm independently. We used chi square feature selection to determine relevant features from RGB histogram. Further, we used and evaluated those relevant features in a classification system, using K-Nearest Neighbor (KNN) as classifier. In this paper we show that by conducting feature selection techniques combined with KNN we would be able to prune non-relevant intensities value of Red, Green, and Blue channel. Furthermore, we use the relevant subset of features to identify intensities range of RGB channel that was needed to represent 32 subcategories fruit image efficiently.","PeriodicalId":426454,"journal":{"name":"2015 International Conference on Electrical Engineering and Informatics (ICEEI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121692822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Efficacy of Arabic named-entity recognition 阿拉伯语命名实体识别的有效性

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352553

Suhad Al-Shoukry, N. Omar

引用次数: 0

Preliminary study disruption in small and medium enterprise supply chain 中小企业供应链中断的初步研究

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352475

Nur Amlya Binti Abd Majid, Nur Fazidah Binti Elias, N. S. Ashaari, Hazura Binti Mohamed

引用次数: 1

MASH Delta Sigma ADC layout for dual mode GSM & WLAN application 用于双模GSM和WLAN应用的MASH Delta Sigma ADC布局

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352463

Clement Christopher, Adityo Prabowo, M. Juliani, A. H. Salman, A. Fuad Mas'ud

{"title":"MASH Delta Sigma ADC layout for dual mode GSM & WLAN application","authors":"Clement Christopher, Adityo Prabowo, M. Juliani, A. H. Salman, A. Fuad Mas'ud","doi":"10.1109/ICEEI.2015.7352463","DOIUrl":"https://doi.org/10.1109/ICEEI.2015.7352463","url":null,"abstract":"Analog to Digital Converter (ADC) is a component which transforms analog signals into digital signals. This paper focused on designing oversampling ADC with Delta-Sigma modulator which will be used in GSM and WLAN baseband communication system. The proposed Delta-Sigma ADC is divided into three main parts, which are pre-processing, modulator, and post-processing modules. Pre-processing module has important role in converting the input signal, which has continuous value continuous time characteristic, to be discrete time continuous value signal. Modulator is needed to process the signal from pre-processing module to be pulse signal, while post-processing module will convert the pulse signal into digital signal. The pre-processing part is implemented by sample and hold circuit. Modulator is designed using cascaded modulator topology - a number of four modulators are cascaded with MASH 2-1-1-1 configuration. Each modulator's block has feedback topology with 1-bit quantizer and works in discrete time domain. Hence, ADC system is implemented in layout of 180 nm technology, which consists of OTA, capacitor, comparator, and digital logic circuit. Decimation Filter of 5-stage CIC filter is needed for the implementation of postprocessing module.","PeriodicalId":426454,"journal":{"name":"2015 International Conference on Electrical Engineering and Informatics (ICEEI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130919881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

FPGA implementation of CORDIC algorithms for sine and cosine generator 用FPGA实现CORDIC算法的正弦和余弦发生器

2015 International Conference on Electrical Engineering and Informatics (ICEEI) Pub Date : 2015-12-17 DOI: 10.1109/ICEEI.2015.7352460

Antonius P. Renardy, Nur Ahmadi, A. Fadila, Naufal Shidqi, T. Adiono

{"title":"FPGA implementation of CORDIC algorithms for sine and cosine generator","authors":"Antonius P. Renardy, Nur Ahmadi, A. Fadila, Naufal Shidqi, T. Adiono","doi":"10.1109/ICEEI.2015.7352460","DOIUrl":"https://doi.org/10.1109/ICEEI.2015.7352460","url":null,"abstract":"Trigonometric-related calculations which are widely found in a broad range of applications can be performed by using COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of conventional CORDIC algorithm with pipelined architecture and Virtually Scaling-Free Adaptive (VSFA) CORDIC. All designs are implemented in Verilog and synthesized by using Altera Quartus II with FPGA DE2 as target board. The pipelined CORDIC consumes 1,103 logic element, 33.32 ns latency, and 420.17 MHz maximum frequency, while VSFA CORDIC utilizes 2,109 logic element, 34.96 ns latency, and 343.29 MHz maximum frequency. Both designs are used to generate sine and cosine wave between -π and π which result in maximum error of 8.095 ×2-13 for pipelined CORDIC and 9.183 × 2-13 for VSFA CORDIC. Based on performance comparison in term of area multiplied by delay (A × T), our pipelined CORDIC is superior among other designs.","PeriodicalId":426454,"journal":{"name":"2015 International Conference on Electrical Engineering and Informatics (ICEEI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129492922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9