FPGA implementation of CORDIC algorithms for sine and cosine generator

Trigonometric-related calculations which are widely found in a broad range of applications can be performed by using COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of conventional CORDIC algorithm with pipelined architecture and Virtually Scaling-Free Adaptive (VSFA) CORDIC. All designs are implemented in Verilog and synthesized by using Altera Quartus II with FPGA DE2 as target board. The pipelined CORDIC consumes 1,103 logic element, 33.32 ns latency, and 420.17 MHz maximum frequency, while VSFA CORDIC utilizes 2,109 logic element, 34.96 ns latency, and 343.29 MHz maximum frequency. Both designs are used to generate sine and cosine wave between -π and π which result in maximum error of 8.095 ×2-13 for pipelined CORDIC and 9.183 × 2-13 for VSFA CORDIC. Based on performance comparison in term of area multiplied by delay (A × T), our pipelined CORDIC is superior among other designs.