2009 International Test Conference最新文献_第3页

Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry 边界扫描采用-一个行业快照，重点是半导体行业

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355673

P. B. Geiger, S. Butkovich

引用次数: 11

Fast circuit topology based method to configure the scan chains in Illinois Scan architecture 基于快速电路拓扑的伊利诺伊扫描结构扫描链配置方法

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355661

Swapneel Donglikar, Mainak Banga, M. Chandrasekar, M. Hsiao

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引用次数: 10

Compression based on deterministic vector clustering of incompatible test cubes 基于不兼容测试数据集的确定性向量聚类压缩

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355555

Grzegorz Mrugalski, N. Mukherjee, J. Rajski, Dariusz Czysz, J. Tyszer

引用次数: 29

Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing 动态任意抖动注入方法在6.5Gb/s伺服器测试

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355735

Tasuku Fujibe, M. Suda, Kazuhiro Yamamoto, Y. Nagata, Kazuhiro Fujita, D. Watanabe, T. Okayasu

引用次数: 12

At-speed test on the QorIQTM P2020 platform 在QorIQTM P2020平台上进行高速测试

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355588

Colin D. Renfrew, Brian Booth, Shweta Latawa, R. Woltenberg, C. Pyron

引用次数: 0

Test infrastructures evaluation at transaction level 在事务级别进行测试基础设施评估

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355830

S. Carlo, N. Hatami, P. Prinetto

引用次数: 1

Thermal characterization of BIST, scan design and sequential test methodologies BIST的热特性，扫描设计和顺序测试方法

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355733

M. O. Simsir, N. Jha

{"title":"Thermal characterization of BIST, scan design and sequential test methodologies","authors":"M. O. Simsir, N. Jha","doi":"10.1109/TEST.2009.5355733","DOIUrl":"https://doi.org/10.1109/TEST.2009.5355733","url":null,"abstract":"It is a well known fact that during testing of a complex integrated circuit (IC), power consumption can far exceed the values reached during its normal operation. High power consumption, combined with limited cooling support, leads to overheating of ICs. This can cause permanent damage to the chip or can invalidate test results due to changes in the path delay. Therefore, even good chips can fail the test. To prevent this problem, a methodology to generate the thermal profile of chips during test is needed. If such profiles are provided beforehand, temperature-aware testing techniques can be devised. In this paper, we address this problem by presenting a methodology for thermally characterizing circuits under test. In our methodology, first, the test sequences for each targeted test strategy, namely, built-in self-test (BIST), scan design and sequential test generation, are generated automatically. Then, power profiles are extracted by using the switching activity information obtained from simulations. Finally, a very fast thermal profiling tool is used to produce the final thermal profiles. To the best of our knowledge, this is the first work on characterizing the thermal effects of different test methods. Such a thermal characterization can be leveraged for temperature-aware system-on-chip (SoC) test scheduling. Our experimental results present the maximum temperature values attained when using different testing techniques on several benchmarks. Results also demonstrate that low power testing techniques are not necessarily temperature-aware.","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126577520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Power scan: DFT for power switches in VLSI designs 功率扫描:用于VLSI设计中的功率开关的DFT

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355631

B. Bai, C. Li, A. Kifli, E. Tsai, Kun-Cheng Wu

引用次数: 0

Scalable and efficient integrated test architecture 可伸缩且高效的集成测试架构

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355811

M. Portolan, Suresh Goyal, B. G. V. Treuren

引用次数: 0

What is IEEE P1149.8.1 and why? 什么是IEEE P1149.8.1，为什么?

2009 International Test Conference Pub Date : 2009-12-18 DOI: 10.1109/TEST.2009.5355837

K. Parker, J. Burgess

引用次数: 1