功率扫描:用于VLSI设计中的功率开关的DFT

2009 International Test Conference Pub Date : 2009-12-18 DOI:10.1109/TEST.2009.5355631

B. Bai, C. Li, A. Kifli, E. Tsai, Kun-Cheng Wu

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引用次数: 0

摘要

这张海报介绍了Power Scan，一种用于VLSI设计中电源开关的可测试性设计。它测量IR下降在功能模式和检测泄漏电流在睡眠模式。功率扫描以较小的面积开销为代价，降低了测试成本。

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Power scan: DFT for power switches in VLSI designs

This poster presents Power Scan, a design-for-testability for power switches in VLSI designs. It measures IR drop in function mode and detects leakage current in sleep mode. Power Scan reduces the test cost at the price of small area overhead.

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2009 International Test Conference

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