Thermal characterization of BIST, scan design and sequential test methodologies

Abstract

It is a well known fact that during testing of a complex integrated circuit (IC), power consumption can far exceed the values reached during its normal operation. High power consumption, combined with limited cooling support, leads to overheating of ICs. This can cause permanent damage to the chip or can invalidate test results due to changes in the path delay. Therefore, even good chips can fail the test. To prevent this problem, a methodology to generate the thermal profile of chips during test is needed. If such profiles are provided beforehand, temperature-aware testing techniques can be devised. In this paper, we address this problem by presenting a methodology for thermally characterizing circuits under test. In our methodology, first, the test sequences for each targeted test strategy, namely, built-in self-test (BIST), scan design and sequential test generation, are generated automatically. Then, power profiles are extracted by using the switching activity information obtained from simulations. Finally, a very fast thermal profiling tool is used to produce the final thermal profiles. To the best of our knowledge, this is the first work on characterizing the thermal effects of different test methods. Such a thermal characterization can be leveraged for temperature-aware system-on-chip (SoC) test scheduling. Our experimental results present the maximum temperature values attained when using different testing techniques on several benchmarks. Results also demonstrate that low power testing techniques are not necessarily temperature-aware.