Proceedings of the 2022 International Symposium on Physical Design最新文献_第5页

A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction 一种避障直线斯坦纳树构建的强化学习智能体

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506721

Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I. Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, M. Chao

{"title":"A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction","authors":"Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I. Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, M. Chao","doi":"10.1145/3505170.3506721","DOIUrl":"https://doi.org/10.1145/3505170.3506721","url":null,"abstract":"This paper presents a router, which tackles a classic algorithm problem in EDA, obstacle-avoiding rectilinear Steiner minimum tree (OARSMT), with the help of an agent trained by our proposed policy-based reinforcement-learning (RL) framework. The job of the policy agent is to select an optimal set of Steiner points that can lead to an optimal OARSMT based on a given layout. Our RL framework can iteratively upgrade the policy agent by applying Monte-Carlo tree search to explore and evaluate various choices of Steiner points on various unseen layouts. As a result, our policy agent can be viewed as a self-designed OARSMT algorithm that can iteratively evolves by itself. The initial version of the agent is a sequential one, which selects one Steiner point at a time. Based on the sequential agent, a concurrent agent can then be derived to predict all required Steiner points with only one model inference. The overall training time can be further reduced by applying geometrically symmetric samples for training. The experimental results on single-layer 15x15 and 30x30 layouts demonstrate that our trained concurrent agent can outperform a state-of-the-art OARSMT router on both wire length and runtime.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114147044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The Need for Speed: From Electric Supercars to Cloud Bursting for Design 对速度的需求:从电动超级跑车到云爆设计

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511033

Dean Drako

引用次数: 1

Session details: Session 11: Lifetime Achievement Commemoration for Ricardo Reis 会议详情:第十一场:里卡多·赖斯终身成就纪念活动

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531645

Jose Luiz Guntzel

引用次数: 0

Session details: Session 15: Global Placement, Macro Placement, and Legalization 会话详细信息:会话15:全局放置，宏观放置和合法化

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531649

J. Shinnerl

引用次数: 0

Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble 使用来自不同数据源的机器学习预测的拥塞和定时感知宏放置:跨设计模型适用性和识别集成

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506722

Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, M. E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota

{"title":"Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble","authors":"Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, M. E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota","doi":"10.1145/3505170.3506722","DOIUrl":"https://doi.org/10.1145/3505170.3506722","url":null,"abstract":"Modern very large-scale integration (VLSI) designs typically use a lot of macros (RAM, ROM, IP) that occupy a large portion of the core area. Also, macro placement being an early stage of the physical design flow, followed by standard cell placement, physical synthesis (place-opt), clock tree synthesis and routing, etc., has a big impact on the final quality of result (QoR). There is a need for Electronic Design Automation (EDA) physical design tools to provide predictions for congestion, timing, and power etc., with certainty for different macro placements before running time-consuming flows. However, the diversity of IC designs that commercial EDA tools must support and the limited number of similar designs that can provide training data, make such machine learning (ML) predictions extremely hard. Because of this, ML models usually need to be completely retrained for unseen designs to work properly. However, collecting full flow macro placement ML data is time consuming and impractical. To make things worse, common ML methods, such as regression, support vector machine (SVM), random forest (RF), neural network (NN) in general, lack a good estimation of prediction accuracy or confidence and lack debuggability for cross-design applications. In this paper, we present a novel discerning ensemble technique for cross-design ML prediction for macro placement. We developed our solution based on a large number of designs with different design styles and technology nodes, and tested the solution on 8 leading-edge industry designs and achieved comparable or even better results in a few hours (per design) than manual placement results that take many engineers weeks or even months to achieve. Our method shows great promise for many ML problems in EDA applications, or even in other areas.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130091670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Session details: Session 1: Opening Session and First Keynote 会议详情:第一部分:开幕式和第一主题演讲

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531635

L. Behjat, Stephen Yang

引用次数: 0

Session details: Session 6: Third Keynote 会议详情:第6部分:第三主题演讲

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531640

C. Alpert

引用次数: 0

Challenges for Automating Package Routing 自动化包路由的挑战

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511474

Wen-Hao Liu, Bing Chen, Hua-Yu Chang, Gary Lin, Zi-Shen Lin

引用次数: 2

The Cerebras CS-2: Designing an AI Accelerator around the World's Largest 2.6 Trillion Transistor Chip Cerebras CS-2:围绕世界上最大的2.6万亿晶体管芯片设计人工智能加速器

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511036

J. Fricker

引用次数: 2

Hardware Security: Physical Design versus Side-Channel and Fault Attacks 硬件安全:物理设计与侧信道和故障攻击

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3513089

I. Verbauwhede

{"title":"Hardware Security: Physical Design versus Side-Channel and Fault Attacks","authors":"I. Verbauwhede","doi":"10.1145/3505170.3513089","DOIUrl":"https://doi.org/10.1145/3505170.3513089","url":null,"abstract":"What is \"hardware\" security? How can we improve trustworthiness in hardware circuits? Is there a design method for secure hardware design? To answer these questions, different communities have different expectations of trusted (expecting trustworthy) hardware components upon which they start to build a secure system. At the same time, electronics shrink: sensor nodes, IOT devices, smart electronics are becoming more and more available. In the past, adding security was only a concern for locked server rooms or now cloud servers. However, these days, our portable devices contain highly private and secure information. Adding security and cryptography to these often very resource constraint devices is a challenge. Moreover, they can be subject to physical attacks, including side-channel and fault attacks [1][2]. This presentation aims at bringing some order in the chaos of expectations by introducing the importance of a design methodology for secure design [3][5]. We will illustrate the capabilities of current side EM and laser fault passive and active attacks. In this context, we will also reflect on the role of physical design, place and route [4][6].","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133996551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0