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Proceedings of the 2022 International Symposium on Physical Design最新文献

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Session details: Session 16: Sixth Keynote 会议详情:第16部分:第六主题演讲
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531650
A. Joshi
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引用次数: 0
Session details: Session 5: Second Keynote 会议详情:第5部分:第二主题演讲
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531639
Louis K. Scheffer
{"title":"Session details: Session 5: Second Keynote","authors":"Louis K. Scheffer","doi":"10.1145/3531639","DOIUrl":"https://doi.org/10.1145/3531639","url":null,"abstract":"","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114194834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving Chip Design Performance and Productivity Using Machine Learning 利用机器学习提高芯片设计性能和生产效率
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511475
N. Hanchate
{"title":"Improving Chip Design Performance and Productivity Using Machine Learning","authors":"N. Hanchate","doi":"10.1145/3505170.3511475","DOIUrl":"https://doi.org/10.1145/3505170.3511475","url":null,"abstract":"Engineering teams are always under pressure to deliver increasingly aggressive power, performance and area (PPA) goals, as fast as possible, on many concurrent projects. Chip designers often spend significant time tuning the implementation flow for each project to meet these goals. Cadence Cerebrus machine learning chip design flow optimization automates this whole process, delivering better PPA much more quickly. During this presentation Cadence will discuss Cerebrus machine learning and distributed computing techniques which enable RTL to GDS flow optimization, delivering better engineering productivity and design performance.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Session details: Session 7: Prototyping, Packaging, and Integration 会议细节:会议7:原型、包装和集成
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531641
Tiago Reimann
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引用次数: 0
Analog Synthesis - The Deterministic Way 模拟合成——确定性方法
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511043
H. Graeb
{"title":"Analog Synthesis - The Deterministic Way","authors":"H. Graeb","doi":"10.1145/3505170.3511043","DOIUrl":"https://doi.org/10.1145/3505170.3511043","url":null,"abstract":"While the majority of research in design automation for analog circuits has been relying on statistical solution approaches, deterministic approaches are an attractive alternative. This paper gives a few examples of deterministic methods for sizing, structural synthesis and layout synthesis of analog circuits, which have been developed over the past decades. It starts from the so-called characteristic boundary curve for interactive parameter optimization, and ends at recent approaches for structural synthesis of operational amplifiers based on functional block composition. A deterministic approach to analog placement and to yield optimization will also be described. The central role of structural analysis of circuit netlists in these approaches will be explained. A summary of the underlying mindset of analog design automation and an outlook on future opportunities for deterministic sizing and layout synthesis concludes the paper.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131440010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps 模拟/混合信号布局优化使用最优的井口
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506728
R. S., Meghna Madhusudan, A. Sharma, Jitesh Poojary, Soner Yaldiz, R. Harjani, S. Burns, S. Sapatnekar
{"title":"Analog/Mixed-Signal Layout Optimization using Optimal Well Taps","authors":"R. S., Meghna Madhusudan, A. Sharma, Jitesh Poojary, Soner Yaldiz, R. Harjani, S. Burns, S. Sapatnekar","doi":"10.1145/3505170.3506728","DOIUrl":"https://doi.org/10.1145/3505170.3506728","url":null,"abstract":"Well island generation and well tap placement pose an important challenge in automated analog/mixed-signal (AMS) layout. Well taps prevent latchup within a radius of influence in a well island, and must cover all devices. Automated AMS layout flows typically perform well island generation and tap insertion as a postprocessing step after placement. However, this step is intrusive and potentially alters the placement, resulting in increased area, wire length, and performance degradation. This work develops a graph-based optimization that integrates well island generation, well tap insertion, and placement. Its efficacy is demonstrated within a stochastic placement engine. Experimental results show that this approach generates better area, wire length and performance metrics than traditional methods, at the cost of a marginal runtime degradation.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130186698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Session details: Session 12: Fifth Keynote 会议详情:第12部分:第五主题演讲
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531646
Bei Yu
{"title":"Session details: Session 12: Fifth Keynote","authors":"Bei Yu","doi":"10.1145/3531646","DOIUrl":"https://doi.org/10.1145/3531646","url":null,"abstract":"","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127861355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Session details: Session 14: Panel on Challenges and Approaches in VLSI Routing 会议详情:第14部分:VLSI路由中的挑战和方法小组讨论
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531648
G. Posser
{"title":"Session details: Session 14: Panel on Challenges and Approaches in VLSI Routing","authors":"G. Posser","doi":"10.1145/3531648","DOIUrl":"https://doi.org/10.1145/3531648","url":null,"abstract":"","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123625813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scalability and Generalization of Circuit Training for Chip Floorplanning 芯片布局电路训练的可扩展性和通用化
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511478
Summer Yue, Ebrahim M. Songhori, Wenjie Jiang, Toby Boyd, Anna Goldie, Azalia Mirhoseini, S. Guadarrama
{"title":"Scalability and Generalization of Circuit Training for Chip Floorplanning","authors":"Summer Yue, Ebrahim M. Songhori, Wenjie Jiang, Toby Boyd, Anna Goldie, Azalia Mirhoseini, S. Guadarrama","doi":"10.1145/3505170.3511478","DOIUrl":"https://doi.org/10.1145/3505170.3511478","url":null,"abstract":"Chip floorplanning is a complex task within the physical design process, with more than six decades of research dedicated to it. In a recent paper published in Nature~citemirhoseini2021graph, a new methodology based on deep reinforcement learning was proposed that solves the floorplanning problem for advanced chip technologies with production quality results. The proposed method enables generalization, which means that the quality of placements improves as the policy is trained on a larger number of chip blocks. In this paper, we describe Circuit Training, an open-source distributed reinforcement learning framework that re-implements the proposed methodology in TensorFlow v2.x. We will explain the framework and discuss ways it can be extended to solve other important problems within physical design and more generally chip design. We also show new experimental results that demonstrate the scaling and generalization performance of Circuit Training.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129076388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Physical Design at the Transistor Level Beyond Standard-Cell Methodology 超越标准电池方法的晶体管级物理设计
Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511476
R. Hentschke
{"title":"Physical Design at the Transistor Level Beyond Standard-Cell Methodology","authors":"R. Hentschke","doi":"10.1145/3505170.3511476","DOIUrl":"https://doi.org/10.1145/3505170.3511476","url":null,"abstract":"This talk offers a review of possibilities to explore on VLSI layout beyond traditional standard cell methodology. Existing Physical Design tools strictly avoid any modification to the contents of Standard Cells. Here, a post-processing step based on SAT solvers is proposed to obtain optimal solutions for local transistor level layout synthesis problems. This procedure can be constrained by metrics that ensure that quality is not degraded, and an acceptable and better-quality timing model can be rebuilt for the block. These problems and techniques are open research opportunities in Physical Design as they are not sufficiently explored in the literature and can bring significant improvements to the quality of a VLSI circuit.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121604551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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