Proceedings of the 2022 International Symposium on Physical Design最新文献_第3页

Accelerating the Design and Performance of Next Generation Computing Systems with GPUs 利用gpu加速下一代计算系统的设计和性能

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511041

S. Halepete

{"title":"Accelerating the Design and Performance of Next Generation Computing Systems with GPUs","authors":"S. Halepete","doi":"10.1145/3505170.3511041","DOIUrl":"https://doi.org/10.1145/3505170.3511041","url":null,"abstract":"The last few years have seen an accelerating growth in the demand for new silicon designs, even as the size and complexity of those designs has increased. However, the gains in design productivity necessary to implement these designs efficiently have not kept up. We need more than an order of magnitude increase in design productivity by the end of the decade to keep up with demand. Traditional methods for improving physical design tool capabilities are running out of steam, and there is a strong need for new approaches. Over the last two decades, we have seen other areas of computer science such as computer vision, speech recognition and natural language processing reach similar plateaus in performance, and each has been able to break out of the stall using GPU accelerated computing and machine learning. There is a similar opportunity in EDA but it will require a rethinking of the way these tools are implemented. The talk will cover where the demand for new silicon designs is coming from, what the productivity bottlenecks are, and then describe some advances in GPUs that could enable us to break through these bottlenecks with some examples.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129788400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrating LR Gate Sizing in an Industrial Place-and-Route Flow 在工业地点和路线流中集成LR门尺寸

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511480

D. Chinnery, A. Sharma

{"title":"Integrating LR Gate Sizing in an Industrial Place-and-Route Flow","authors":"D. Chinnery, A. Sharma","doi":"10.1145/3505170.3511480","DOIUrl":"https://doi.org/10.1145/3505170.3511480","url":null,"abstract":"Lagrangian relaxation (LR) based gate sizing is the state-of-the-art gate-sizing approach. Integrating it within a place-and-route (P&R) tool is difficult as LR needs multiple iterations to converge, requiring very fast timing analysis. Gate-sizing is invoked in many P&R flow steps, so it is also unclear where best to use LR sizing. We detail development of a LR gate sizer for an industrial P&R flow. Software architecture and P&R flow needs are discussed. We summarize how we sped up the LR sizer by 3x to resize a million gates per hour, and ensure multi-threaded results are deterministic. LR sizing experiments at the fast WNS/TNS optimization steps in the flow stages before and after clock tree synthesis (CTS) show excellent results: 10% to 20% setup timing total negative slack (TNS) reduction with 11% to 14% less leakage power, or 1% to 3% lower total power (dynamic power + leakage) with a total power objective, and 1% to 3% lower cell area. Worst negative slack (WNS) also improved in 2/3 of designs in pre-CTS. In the full flow, 5% lower leakage, 1% lower total power, and 0.6% lower cell area can be achieved, with roughly neutral impact on other metrics, compared to a high-effort low-power P&R flow baseline.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134112492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Session details: Session 2: Placement, Clock Tree Synthesis, and Optimization 会议细节:会议2:放置，时钟树合成和优化

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531636

Deepashree Sengupta

引用次数: 0

Session details: Session 10: Fourth Keynote 会议详情:第10部分:第四主题演讲

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531644

J. Lienig

引用次数: 0

ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs ART-3D:单片3D集成电路的强化参数调整分析3D放置

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506725

Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo, S. Lim

{"title":"ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs","authors":"Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo, S. Lim","doi":"10.1145/3505170.3506725","DOIUrl":"https://doi.org/10.1145/3505170.3506725","url":null,"abstract":"In this paper, we show that true 3D placement approaches, enhanced with reinforcement learning, can offer further PPA improvements over pseudo-3D approaches. To accomplish this goal, we integrate an academic true 3D placement engine into a commercial-grade 3D physical design flow, creating ART-3D flow (Analytical 3D Placement with Reinforced Parameter Tuning-based 3D flow). We use a reinforcement learning (RL) framework to find optimized placement parameter settings of the true 3D placement engine for a given netlist and perform high-quality 3D placement. We then use an efficient 3D optimization and routing engine based on a commercial place and route (P&R) tool to maintain or improve the benefits reaped from true 3D placement till design signoff. We evaluate our 3D flow by designing several gate-only and processor benchmarks on a commercial 28nm technology node. Our proposed 3D flow involving true 3D placement offers the best PPA results compared to existing 3D P&R flows and reduces power consumption by up to 31%, improves effective frequency by up to 25%, and therefore reduces power-delay product by up to 43% compared with commercial 2D IC design flow. These improvements predominantly come from RL-based parameter tuning, as it improves the performance of the 3D placer by up to 12%.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121266256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Session details: Session 9: Routing 会话详细信息:会话9:Routing

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531643

Jhih-Rong Gao

引用次数: 0

Global Placement Exploiting Soft 2D Regularity 利用软2D规则的全局放置

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506723

Donghao Fang, Boyang Zhang, Hailiang Hu, Wuxi Li, Bo Yuan, Jiang Hu

引用次数: 5

From Hard-Coded Heuristics to ML-Driven Optimization: New Frontiers for EDA 从硬编码启发式到机器学习驱动优化:EDA的新领域

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511799

P. Groeneveld

{"title":"From Hard-Coded Heuristics to ML-Driven Optimization: New Frontiers for EDA","authors":"P. Groeneveld","doi":"10.1145/3505170.3511799","DOIUrl":"https://doi.org/10.1145/3505170.3511799","url":null,"abstract":"The very first Design Automation Conference was held in 1964 when computers were programmed with punch cards. The initial topics were related to automated Printed Circuit Board design, cell placement, and early attempts at transient circuit analysis. The next decades saw the introduction of key graph algorithms and numerical analysis methods. Optimal algorithms and more practical heuristic methods were published. The 1980ies saw the advent of simulated annealing, a universal heuristic optimization method that found many applications. The next decade introduced powerful numerical placement methods for millions of cells. Soon after, physical synthesis was born by combining several incremental synthesis and analysis tools. Today's commercial EDA tools run a very complex design flow that chains together hundreds of algorithms that were developed over 60 decades. Most effort is in the careful fine-tuning of parameters and addressing the complex - and often surprising - algorithmic interactions. This is a difficult trial-and-error process, driven by a small set of benchmarks. Machine Learning methods will take some of the human tuning efforts out of this loop. Some have already found their way in commercial tools. It will take a while before a Machine Learning method fully replaces a 'traditional' EDA algorithm. Each method in the flow has a limited sweet spot and is often run-time critical. On the other hand, conventional algorithms leave only insignificant opportunities for speed up through parallelism. Machine Learning methods may provide the only viable way to unlock the potential of massive cloud computing resources.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"42 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124043359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimized is Not Always Optimal - The Dilemma of Analog Design Automation 优化并不总是最优——模拟设计自动化的困境

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511042

J. Scheible

引用次数: 2

Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement 最小最大位移的线性时间混合单元高度合法化

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506724

Chung-Hsien Wu, Wai-Kei Mak, C. Chu

{"title":"Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement","authors":"Chung-Hsien Wu, Wai-Kei Mak, C. Chu","doi":"10.1145/3505170.3506724","DOIUrl":"https://doi.org/10.1145/3505170.3506724","url":null,"abstract":"Due to the aggressive scaling of advanced technology nodes, multiple-row-height cells have become more and more common in VLSI design. Consequently, the placement of cells is no longer independent among different rows, which makes the traditional row-based legalization techniques obsolete. In this work, we present a highly efficient linear-time mixed-cell-height legalization approach that optimizes both the total cell displacement and the maximum cell displacement. First, a fast window-based cell insertion technique introduced in [4] is applied to obtain a feasible initial row assignment and cell ordering which is known to be good for total displacement consideration. In the second stage, we use an iterative cell swapping algorithm to change the row assignment and the cell order of the critical cells for maximum displacement reduction. Then we develop an optimal linear time DAG-based fixed row and fixed order legalization algorithm to minimize the maximum cell displacement. Finally, we propose a cell shifting heuristic to reduce the total cell displacement without increasing the maximum cell displacement. Using the proposed approach, the quality provided by the global placement can be preserved as much as possible. Compared with the state-of-the-art work [4], experimental results show that our proposed algorithm can reduce the maximum cell displacement by more than 11% on average with similar average cell displacement.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131842393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1