Proceedings of the 2022 International Symposium on Physical Design最新文献

Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning 基于多相正不确定性整定的设计流参数优化

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506727

M. Ziegler, L. Reddy, R. Franch

{"title":"Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning","authors":"M. Ziegler, L. Reddy, R. Franch","doi":"10.1145/3505170.3506727","DOIUrl":"https://doi.org/10.1145/3505170.3506727","url":null,"abstract":"Synthesis and place & route tools are highly leveraged for modern digital design. But, despite continuous improvement in CAD tool performance, products in competitive markets often set PPA (performance, power, area) targets beyond what the tools can natively deliver. These aggressive targets lead to circuit designers attempting to tune a vast number of design flow parameters in search of near-optimal design specific flow recipes. Compounding the complex design flow parameter tuning problem is that many digital design tools exhibit nondeterminism, i.e., run-to-run variation. While CAD tool nondeterminism is typically considered an undesirable behavior, this paper proposes design flow tuning methodologies that take advantage of nondeterminism. We propose techniques that employ a combination of running targeted scenarios multiple times to exploit positive deviations nondeterminism can produce and leverage the best observed runs as seeds for multi-phase tuning. We introduce three seed variants for multi-phase tuning that have a spectrum of characteristics, trading off PPA improvement and reduce run-to-run variation. Our experimental analysis using high-performance industrial designs show that the proposed novel techniques outperform an existing state-of-the-art industrial design flow tuning program across all PPA metrics. Furthermore, our proposed approaches reduce run-to-run variation of the best scenarios, leading to a more predictable design flow.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"25 43","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120835889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration 2.5D/3D异构集成的最新进展和未来挑战

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3512295

T. Karnik

引用次数: 0

On Ensuring Congruency with Implementation During Emulation and Prototyping 在仿真和原型设计中保证与实现的一致性

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3513090

Alex Rabinovitch

引用次数: 0

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies AutoCRAFT:先进FinFET技术中定制电路的布局自动化

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511044

Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, G. Kokai, B. Zimmer, C. T. Gray, Brucek Khailany, D. Pan, Haoxing Ren

引用次数: 3

Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines 能源和计算效率高的比特币矿机时钟设计方法

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506720

Chien-Pang Lu, I. Jiang, Chih-Wen Yang

{"title":"Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines","authors":"Chien-Pang Lu, I. Jiang, Chih-Wen Yang","doi":"10.1145/3505170.3506720","DOIUrl":"https://doi.org/10.1145/3505170.3506720","url":null,"abstract":"Bitcoin mining machines become a new driving force to push the physical limitation of semiconductor process technology. Instead of peak performance, mining machines pursue energy and computation efficiency of implementing cryptographic hash functions. Therefore, the state-of-the-art ASIC design of mining machines adopts near-threshold computing, deep pipelines, and uni-directional data flow. According to these design properties, in this paper, we propose a novel clock reversing tree design methodology for bitcoin mining machines. In the clock reversing tree, the clock of global tree is fed from the last pipeline stage backward to the first one, and the clock latency difference between the local clock roots of two consecutive stages maintains a constant delay. The local tree of each stage is well balanced and keeps the same clock latency. The special clock topology naturally utilizes setup time slacks to gain hold time margins. Moreover, to alleviate the incurred on-chip variations due to near-threshold computing, we maximize the common clock path shared by flip-flops of each individual stage. Finally, we perform inverter pair swap to maintain duty cycle. Experimental results show that our methodology is promising for industrial bitcoin mining designs: Compared with two variation-aware clock network synthesis approaches widely used in modern ASIC designs, our approach can reduce up to 64% clock buffer/inverter usage, 12% clock power, decrease 99% hold time violating paths, and achieve 85% area saving for timing fixing. The proposed clock design methodology is general and applicable to blockchain and other ASICs with deep pipelines and strong data flow.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128155326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Session details: Session 17: ISPD 2022 Contest Results and Closing Remarks 会议详情:第17部分:ISPD 2022竞赛结果和闭幕词

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531651

D. Chinnery

引用次数: 0

Kernel Mapping Techniques for Deep Learning Neural Network Accelerators 深度学习神经网络加速器的核映射技术

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506730

Sarp Özdemir, Mohammad Khasawneh, Smriti Rao, P. Madden

引用次数: 1

Session details: Session 8: 3D IC Design 会议详情:会议8:3D集成电路设计

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531642

L. Feng

引用次数: 0

What's So Hard About (Mixed-Size) Placement? (混合尺寸)布局有什么难的?

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511035

M. Khasawneh, P. Madden

引用次数: 1

Challenges and Approaches in VLSI Routing VLSI路由的挑战与方法

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511477

G. Posser, Evangeline F. Y. Young, S. Held, Yih-Lang Li, D. Pan

引用次数: 1