Proceedings of the 2022 International Symposium on Physical Design最新文献_第6页

Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest 基准安全关闭物理布局:ISPD 2022竞赛

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3511046

J. Knechtel, Jayanth Gopinath, M. Ashraf, Jitendra Bhandari, O. Sinanoglu, R. Karri

{"title":"Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest","authors":"J. Knechtel, Jayanth Gopinath, M. Ashraf, Jitendra Bhandari, O. Sinanoglu, R. Karri","doi":"10.1145/3505170.3511046","DOIUrl":"https://doi.org/10.1145/3505170.3511046","url":null,"abstract":"Computer-aided design (CAD) tools mainly optimize for power, performance, and area (PPA). However, given a large number of serious hardware-security threats that are emerging, future CAD flows must also incorporate techniques for designing secure integrated circuits (ICs). In fact, the stakes are quite high for IC vendors and design companies, as security risks that are not addressed during design time will inevitably be exploited in the field, where vulnerabilities are almost impossible to fix. However, there is currently little to no experience related to designing secure ICs available within the CAD community. For the very first time, this contest seeks to actively engage with the community to close this gap. The theme of this contest is security closure of physical layouts, that is, hardening the physical layouts at design time against threats that are executed post-design time. More specifically, this contest is focused on selected and seminal threats that, once taken in, are relatively simple to approach and mitigate through means of physical design: Trojan insertion and probing as well as fault injection. Acting as security engineers, contest participants will iteratively and proactively evaluate and fix the vulnerabilities of provided benchmark layouts. Benchmarks and submissions are based on the generic DEF format and related files. Thus, participants are free to use any physical-design tools of their choice, helping us to open up the contest to the community at large.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130247620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

LEO: Line End Optimizer for Sub-7nm Technology Nodes LEO:用于7纳米以下技术节点的线端优化器

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506726

Diwesh Pandey, G. Téllez, J. Leland

引用次数: 0

Session details: Session 3: Design Flow Advances with Machine Learning and Lagrangian Relaxation 会议详情:会议3:设计流程与机器学习和拉格朗日松弛的进展

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531637

Ulf Schlichtmann

引用次数: 0

RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement RTL-MP:走向实用、人性化的芯片规划和宏观布局

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3505170.3506731

A. Kahng, R. Varadarajan, Zhiang Wang

{"title":"RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement","authors":"A. Kahng, R. Varadarajan, Zhiang Wang","doi":"10.1145/3505170.3506731","DOIUrl":"https://doi.org/10.1145/3505170.3506731","url":null,"abstract":"In a typical RTL-to-GDSII flow, floorplanning plays an essential role in achieving decent quality of results (QoR). A good floorplan typically requires interaction between the frontend designer, who is responsible for the functionality of the RTL, and the backend physical design engineer. The increasing complexity of macro-dominated designs (especially machine learning accelerators with autogenerated RTL) has made the floorplanning task even more challenging and time-consuming. In this paper, we propose RTL-MP, a novel macro placer which utilizes RTL information and tries to \"mimic\" the interaction between the frontend RTL designer and the backend physical design engineer to produce human-quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures, RTL-MP can capture the dataflow inherent in the RTL and use the dataflow information to guide macro placement. We also apply autotuning to optimize hyperparameter settings based on input designs. We have built RTL-MP based on OpenROAD infrastructure and applied RTL-MP to a set of industrial designs. RTL-MP outperforms state-of-the-art commercial macro placers and achieves QoR similar to that of handcrafted floorplans.","PeriodicalId":417023,"journal":{"name":"Proceedings of the 2022 International Symposium on Physical Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126714886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Session details: Session 13: Advances in Analog and Full Custom Design Automation 会议详情:会议13:模拟和完全定制设计自动化的进展

Proceedings of the 2022 International Symposium on Physical Design Pub Date : 2022-04-13 DOI: 10.1145/3531647

M. Lin

引用次数: 0