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Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)最新文献

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Data acquisition device with packet based communication protocol for engine monitoring 基于分组通信协议的发动机监测数据采集装置
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004086
R. E. Alonso, J. Leffew, S. Shreinivasan, W. Moreno
{"title":"Data acquisition device with packet based communication protocol for engine monitoring","authors":"R. E. Alonso, J. Leffew, S. Shreinivasan, W. Moreno","doi":"10.1109/ICCDCS.2002.1004086","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004086","url":null,"abstract":"In the new trend of high performance motors with highly sophisticated engines and low emission control systems, the data transfer for normal service maintenance and repairs has increased to such a complex level that it requires dedicated computer systems. The proposed basic portable computer design involves normal signal measurements like voltage, resistance, temperature and revolutions per minute of the crankshaft, and the on-board computer data stream acquisition. The objective is a simple device, which is upgradeable and capable of managing the data acquisition (DAQ), of different signals generated by the system and the transfer of information from the actual point of activity to a remote location using the existing communication systems - like serial through a local phone line or DSL. The study presents a simple system design, which is based on an analog-digital signal-processing component, which acts as a DAQ, a microcontroller and a modem that is used as an interface between the remote system and the central data service.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124695405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Raman spectral classification of atherosclerosis using neural networks and discriminant analysis 基于神经网络和判别分析的动脉粥样硬化拉曼光谱分类
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004078
A. R. de Paula, S. Sathaiah
{"title":"Raman spectral classification of atherosclerosis using neural networks and discriminant analysis","authors":"A. R. de Paula, S. Sathaiah","doi":"10.1109/ICCDCS.2002.1004078","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004078","url":null,"abstract":"Raman spectroscopy is a powerful non-destructive technique and has a high potential for in vivo diagnosis applications of atherosclerotic plaques in human arteries. For such real time clinical applications, a rapid collection and analysis of the data is needed. One of the major problems with rapid data collection is that the noise generated by the detector (even with one of the most advanced versions) has the same level as the Raman signal from the tissue which makes the analysis difficult. In this paper, different processing techniques for compressing the spectrum vector collected with very short time scales (/spl sim/msec) and its rapid classification methods were analyzed. The accomplished results demonstrated that the classification error was smaller than 5%, even with the data collection times as low as 50 msec, when the wavelet transformation was utilized to compress the input vector and the classification methods based on either neural network or discriminant analysis were applied.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128197459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CMOS downsizing and high-K gate insulator technology CMOS小型化和高k栅极绝缘体技术
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004072
H. Iwai, S. Ohmi
{"title":"CMOS downsizing and high-K gate insulator technology","authors":"H. Iwai, S. Ohmi","doi":"10.1109/ICCDCS.2002.1004072","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004072","url":null,"abstract":"Downscaling of MOSFETs is the driving force of the development of new generation CMOS ULSIs. Now, gate lengths of the transistors have reached sub-100 nm in production and 15 nm in research. However, many difficulties are expected to further downsizing of the device dimensions. The biggest difficulty at this moment is the thinning of the gate oxide. In this paper, problems the downsizing and expected solutions in particular those for the gate oxide thinning for miniaturized CMOS ULSI devices are explained.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121881933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The interaction of hot electrons and hot holes on the degradation of P-channel metal oxide semiconductor field effect transistors 热电子与热空穴相互作用对p沟道金属氧化物半导体场效应晶体管退化的影响
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004038
Z.J. Yang, F. Guarín, S. Rauch
{"title":"The interaction of hot electrons and hot holes on the degradation of P-channel metal oxide semiconductor field effect transistors","authors":"Z.J. Yang, F. Guarín, S. Rauch","doi":"10.1109/ICCDCS.2002.1004038","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004038","url":null,"abstract":"The hot carrier degradation mechanisms for P Channel metal-oxide-semiconductor (MOS) field effect transistor (PFET) has been investigated. We have established that the dominant hot carrier degradation mechanism for PFET damage changes depending on stress conditions. The coexistence and interaction of hot electrons and hot holes is reported. At the accelerated stress condition where both hot electrons and hot holes exist, the observed hot carrier degradation exhibits a different behavior from that seen in the case when the hot electrons or hot holes are considered separately. A high defect generation rate is reported at the coexistence conditions. We attribute this behavior to the interaction mechanism between hole electrons and hot holes. The electron traps caused by hot electrons recombine with hot holes and facilitate a higher hole trap generation rate. Contrary to conventional thinking we report that the worst case hot carrier degradation degradation condition is not at high Vg but in the coexistence regime.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116557968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design, optimization and fabrication of a tanh/sinh-type bipolar transconductor with maximum linearity 具有最大线性度的tanh/sinh型双极晶体管的设计、优化和制造
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004020
R. Salazar, J. Finol, F. Garcia Sanchez, A. Ortiz-Conde
{"title":"Design, optimization and fabrication of a tanh/sinh-type bipolar transconductor with maximum linearity","authors":"R. Salazar, J. Finol, F. Garcia Sanchez, A. Ortiz-Conde","doi":"10.1109/ICCDCS.2002.1004020","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004020","url":null,"abstract":"We have designed, optimized and fabricated a bipolar transconductor with maximum static transfer function linearity. The optimization was based on an analytic function that corresponds to the integral nonlinearity of the circuit. This transconductor is composed of two parallel-connected non-linear blocks: a hyperbolic tangent-type transconductor and hyperbolic sine-type transconductor. The transconductor was fabricated using 0.5 /spl mu/m BiCMOS mixed-signal process. A minimum THD value of 0.2% was obtained with a 100 /spl mu/s transconductance up to a maximum input voltage swing of 50 mV peak.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132463181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fully integrated programmable Howland current source for sensors excitation 完全集成可编程Howland电流源传感器励磁
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004016
Marcos Mauricio Pelicia, Carlos A. dos Reis
{"title":"Fully integrated programmable Howland current source for sensors excitation","authors":"Marcos Mauricio Pelicia, Carlos A. dos Reis","doi":"10.1109/ICCDCS.2002.1004016","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004016","url":null,"abstract":"In this paper a fully integrated implementation of the classical Howland current source is presented as a compact solution for exciting resistive and piezoresistive sensors. This circuit, which is part of a programmable signal conditioning microsystem, described elsewhere, is treated as a module that is capable of providing a voltage-adjustable current whose full-scale is 10 mA. Experimental results from samples manufactured in 0.8 /spl mu/m CMOS have shown that the circuit features a full-scale nonlinearity of 0.042% powered by a supply voltage of 5 V. The measured frequency response using a 50 /spl Omega/ resistive load rolls off at 228 kHz, which is in excess of the predicted applications.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114655086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
FPGA board for real time vision development systems 用于实时视觉开发系统的FPGA板
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004106
P. C. Arribas, F. Maciá
{"title":"FPGA board for real time vision development systems","authors":"P. C. Arribas, F. Maciá","doi":"10.1109/ICCDCS.2002.1004106","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004106","url":null,"abstract":"Describes an FPGA based system for real time vision applications at a robotics vision laboratory. It contains an ALTERA FPGA (20K100), an interface with a digital camera, three VRAM memories to contain the data input and some output memories (a VRAM and a EDO) to contain the results. The aim of this system is to develop and test vision algorithms, such as image compression, optical flow calculation with differential and correlation methods and to hold applications that use previous calculated optical flow, like image invariants detection. The designed system is able to connect the digital camera, or the FPGA output (results of algorithms) to a PC, through its ports USB, IEEE 1394 or CENTRONICS. It also has an expansion connector to make possible the expansion of the system, with some elements of the process, for instance one system would calculate the optical flow of the input images and another system would calculate the focus of expansion in the image and the time to impact in the scene.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132828486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
An alternative method to determine effective channel length and parasitic series resistance of LDD MOSFET's 一种确定LDD MOSFET的有效沟道长度和寄生串联电阻的替代方法
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004025
R. Torres‐Torres, R. Murphy‐Arteaga
{"title":"An alternative method to determine effective channel length and parasitic series resistance of LDD MOSFET's","authors":"R. Torres‐Torres, R. Murphy‐Arteaga","doi":"10.1109/ICCDCS.2002.1004025","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004025","url":null,"abstract":"A new method to determine MOSFET effective channel length and parasitic source/drain series resistance is presented in this paper. Compared to previously reported methods, the one presented here allows the determination of these parameters simultaneously and as a function of gate voltage. The method is based on the iterative solution of a derived linear-region drain current relation. The method is validated with experimental data taken from submicron LDD MOSFETs, and compared with several previously published methods.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116077424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Percentage Area Difference (PAD) as a measure of distortion and its use in Maximum Enclosed Area (MEA), a new ECG signal compression algorithm 百分比面积差(PAD)作为一种新的心电信号压缩算法及其在最大封闭区域(MEA)中的应用
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004092
A.C. D'Ambrosio, A. Ortiz-Conde, F. Garcia Sanchez
{"title":"Percentage Area Difference (PAD) as a measure of distortion and its use in Maximum Enclosed Area (MEA), a new ECG signal compression algorithm","authors":"A.C. D'Ambrosio, A. Ortiz-Conde, F. Garcia Sanchez","doi":"10.1109/ICCDCS.2002.1004092","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004092","url":null,"abstract":"A new measure of distortion, named the Percentage Area Difference (PAD), is proposed as an alternative to existing ways of evaluating the performance of Electrocardiogram (ECG) signal lossy compression. This novel distortion measure, which corresponds to the area enclosed between the original and the reconstructed signal, is also used as a maximum tolerance comparison criterion in a new non-uniform sampling method, designated Maximum Enclosed Area algorithm (MEA), which is proposed here for direct ECG signal compression.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116768633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
The use of T-CAD tool for yield improvement on fast-switching power rectifiers 利用T-CAD工具提高快速开关电源整流器的良率
Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) Pub Date : 2002-08-07 DOI: 10.1109/ICCDCS.2002.1004029
P. Garcia, J. L. del Valle, Y. Matsumoto, K. Akinade, H.E. Aldrete
{"title":"The use of T-CAD tool for yield improvement on fast-switching power rectifiers","authors":"P. Garcia, J. L. del Valle, Y. Matsumoto, K. Akinade, H.E. Aldrete","doi":"10.1109/ICCDCS.2002.1004029","DOIUrl":"https://doi.org/10.1109/ICCDCS.2002.1004029","url":null,"abstract":"Technological changes for mature devices are not as straightforward as one wishes. Reducing learning curve time is a must to remain competitive in the market share. This paper present a method based on device physics and simulation using T-CAD tool coupled with a virtual DOE technique to assess yield improvement and learning curve reduction. The method is applied to platinum doped fast switching power rectifiers.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124718135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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