An alternative method to determine effective channel length and parasitic series resistance of LDD MOSFET's

Abstract

A new method to determine MOSFET effective channel length and parasitic source/drain series resistance is presented in this paper. Compared to previously reported methods, the one presented here allows the determination of these parameters simultaneously and as a function of gate voltage. The method is based on the iterative solution of a derived linear-region drain current relation. The method is validated with experimental data taken from submicron LDD MOSFETs, and compared with several previously published methods.