{"title":"一种确定LDD MOSFET的有效沟道长度和寄生串联电阻的替代方法","authors":"R. Torres‐Torres, R. Murphy‐Arteaga","doi":"10.1109/ICCDCS.2002.1004025","DOIUrl":null,"url":null,"abstract":"A new method to determine MOSFET effective channel length and parasitic source/drain series resistance is presented in this paper. Compared to previously reported methods, the one presented here allows the determination of these parameters simultaneously and as a function of gate voltage. The method is based on the iterative solution of a derived linear-region drain current relation. The method is validated with experimental data taken from submicron LDD MOSFETs, and compared with several previously published methods.","PeriodicalId":416680,"journal":{"name":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"An alternative method to determine effective channel length and parasitic series resistance of LDD MOSFET's\",\"authors\":\"R. Torres‐Torres, R. Murphy‐Arteaga\",\"doi\":\"10.1109/ICCDCS.2002.1004025\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new method to determine MOSFET effective channel length and parasitic source/drain series resistance is presented in this paper. Compared to previously reported methods, the one presented here allows the determination of these parameters simultaneously and as a function of gate voltage. The method is based on the iterative solution of a derived linear-region drain current relation. The method is validated with experimental data taken from submicron LDD MOSFETs, and compared with several previously published methods.\",\"PeriodicalId\":416680,\"journal\":{\"name\":\"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)\",\"volume\":\"113 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCDCS.2002.1004025\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCDCS.2002.1004025","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An alternative method to determine effective channel length and parasitic series resistance of LDD MOSFET's
A new method to determine MOSFET effective channel length and parasitic source/drain series resistance is presented in this paper. Compared to previously reported methods, the one presented here allows the determination of these parameters simultaneously and as a function of gate voltage. The method is based on the iterative solution of a derived linear-region drain current relation. The method is validated with experimental data taken from submicron LDD MOSFETs, and compared with several previously published methods.