2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第3页

Predictive Fault Grouping based on Faulty AC Matrices 基于故障交流矩阵的预测故障分组

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417072

Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, André Alberts, F. Fummi

{"title":"Predictive Fault Grouping based on Faulty AC Matrices","authors":"Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, André Alberts, F. Fummi","doi":"10.1109/DDECS52668.2021.9417072","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417072","url":null,"abstract":"In this article, a predictive fault grouping based on the collection of faulty AC matrices at fault-free operating points is presented as a means to approximate the final distribution of faults in equivalence classes using a minimal computational effort. The method is computationally cheap because it avoids performing DC or transient simulations with faults injected and limits itself only to AC simulations with faults activated. The technique provides an approximation, since it does not characterize faults at the corresponding faulty operating point but instead looks at how they would modify the fault-free operating point once injected.The approximate grouping achieves an excellent correlation to the final classification based on the comparison of faulty transient wave-forms. It is not meant as a substitute for the traditional fault injection simulations but as a support to decision making. It allows prioritizing faults to characterize the possible failure modes with a minimum number of fault injections, pushing out fault injections which are estimated to marginally increase the learning.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130230640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories 基于片外存储器优化的TSS算法的高速状态分组分类器

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417060

Michal Orsák, Tomás Benes

{"title":"High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories","authors":"Michal Orsák, Tomás Benes","doi":"10.1109/DDECS52668.2021.9417060","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417060","url":null,"abstract":"We present a modular out-of-order architecture for stateful packet classification. The architecture uses DDR4 SDRAM memory to store rules and their state information to support millions of rules. The memory access pattern generated by network traffic significantly degrades the performance of the DDR4. Our architecture contains a cache and aggregation queues to negate this effect. Additionally, the memory subsystem supports a read cancellation and uses an out-of-order pipeline to maximize the main memory’s effectiveness further. The rule set update is implemented as a non-blocking operation and can be interleaved with lookup operations without any performance decrease, leading to the same execution time for rule update and rule lookup. The architecture is optimized for the modern datacenter’s network traffic and a small on-chip memory footprint, making it suitable as an accelerator for the Open vSwitch. As a result, our novel architecture configured with 1 million exact match rules can process traffic up to 202 Gbit/s (300 Mp/s) in average case and 51 Gbit/s (76 Mp/s) in the worst case with the use of a common dual-channel 64 bit DDR4-2666 MHz. It uses fewer FPGA resources (excluding cache memory) than the well-known de facto industry standard Xilinx MIG DDR4 controllers. Our proposed architecture enables commodity FPGA cards commonly equipped with DDR4 to process 100 Gbit/s which results in a significant cost reduction of a 100G SmartNICs.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"59 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120860100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Synthesis of approximate circuits for LUT-based FPGAs 基于lut的fpga近似电路的合成

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417066

Z. Vašíček

{"title":"Synthesis of approximate circuits for LUT-based FPGAs","authors":"Z. Vašíček","doi":"10.1109/DDECS52668.2021.9417066","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417066","url":null,"abstract":"Approximate computing is an emerging paradigm that trades the accuracy of computation to achieve gain in terms of design area, critical path delay and/or power consumption. There is a rich body of literature showing that the approximate hardware components serving as basic building blocks for energy-efficient implementation of complex systems offer a remarkable gain in efficiency and/or performance in exchange for small losses in output quality. However, recent studies revealed that the approximate components optimized mainly for ASICs offer asymmetric gain when used in FPGAs. In this work, we present an iterative design method for automated synthesis of elementary approximate components natively optimized for usage in LUT-based FPGAs. The method takes into account the number of LUTs and LUT-level propagation delay instead of the number of gates and logic levels typically considered in other works. Using this method, we synthesized various approximate adders (up to 64-bit) and multipliers (8-bit and 16-bit). Compared to the current state-of-the-art, our designs achieve better trade-off when considered the worst case absolute error, number of LUTs and propagation delay. The discovered approximate adders and multipliers are available online in the form of Verilog netlists consisting of 4, 5 and 6-input LUTs.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131117369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the Functional Test of Special Function Units in GPUs gpu中特殊功能单元的功能测试

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417025

Juan-David Guerrero-Balaguera, J. E. R. Condia, M. Reorda

{"title":"On the Functional Test of Special Function Units in GPUs","authors":"Juan-David Guerrero-Balaguera, J. E. R. Condia, M. Reorda","doi":"10.1109/DDECS52668.2021.9417025","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417025","url":null,"abstract":"The Graphics Processing Units (GPUs) usage has extended from graphic applications to others where their high computational power is exploited (e.g., to implement Artificial Intelligence algorithms). These complex applications usually need highly intensive computations based on floating-point transcendental functions. GPUs may efficiently compute these functions in hardware using ad hoc Special Function Units (SFUs). However, a permanent fault in such units could be very critical (e.g., in safety-critical automotive applications). Thus, test methodologies for SFUs are strictly required to achieve the target reliability and safety levels. In this work, we present a functional test method based on a Software-Based Self-Test (SBST) approach targeting the SFUs in GPUs. This method exploits different approaches to build a test program and applies several optimization strategies to exploit the GPU parallelism to speed up the test procedure and reduce the required memory. The effectiveness of this methodology was proven by resorting to an open-source GPU model (FlexGripPlus) compatible with NVIDIA GPUs. The experimental results show that the proposed technique achieves 90.75% of fault coverage and up to 94.26% of Testable Fault Coverage, reducing the required memory and test duration with respect to pseudorandom strategies proposed by other authors.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125714505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation 基于自适应处理器的容错高效系统设计与实现策略

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417023

M. Veleski, M. Hübner, M. Krstic, R. Kraemer

{"title":"Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation","authors":"M. Veleski, M. Hübner, M. Krstic, R. Kraemer","doi":"10.1109/DDECS52668.2021.9417023","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417023","url":null,"abstract":"The contemporary computing systems are facing two major challenges: excessive power consumption and susceptibility to faults. In order to take advantage of techniques that efficiently address these challenges, the classic ASIC design flow requires some modifications. In this paper, we present a simple and convenient strategy for design and implementation of processor-based systems using highly configurable, cross-layer framework that encompasses techniques such as Adaptive Voltage and Frequency Scaling (AVFS) and Triple Modular Redundancy (TMR). The proposed strategy augments the conventional design flow with two additional steps to integrate the framework’s hardware building blocks into the system. Such system is then able to dynamically switch between low power and error resilient operation modes according to the current requirements. By following the proposed strategy, we were able to implement processor-based system that significantly reduces the power consumption / increases the soft error resilience while preserving the performance at negligible area overhead of less than 1%.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125408437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures 基于多核架构并行化的仿真转储加速分析

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417048

D. Appello, P. Bernardi, A. Calabrese, S. Littardi, G. Pollaccia, S. Quer, V. Tancorre, R. Ugioli

{"title":"Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures","authors":"D. Appello, P. Bernardi, A. Calabrese, S. Littardi, G. Pollaccia, S. Quer, V. Tancorre, R. Ugioli","doi":"10.1109/DDECS52668.2021.9417048","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417048","url":null,"abstract":"With the explosion of off-the-shelf SoCs in terms of size and the advent of novel techniques related to failure modes, commercial ATPG and fault simulation engines can often be insufficient to measure the coverage of very specific metrics. In these cases, many researchers firstly store the simulation trace during the analysis phase. Then, they collect the desired statistics during a post-processing step. In this framework, the so-called Value Change Dump (VCD) is a very commonly used file format to record simulation traces. The target of this paper is twofold. From the one hand, we illustrate some Burn-In (BI) related metrics which cannot be evaluated by current commercial fault simulators and ATPG engines. These metrics are indeed based on a post-processing analysis of memory dumps in VCD format. From the other hand, we mitigate the evaluation time and the memory required to analyze huge VCD files by exploiting optimization techniques coming from modern programming features and smart parallelization. Adopting this strategy, we can analyze simulation dumps of more than 250 GBytes in less than one hour, showing improvements of two orders of magnitude over previous tools, with a consequent higher scalability and testability power.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126576185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines 基于wchb的准延迟不敏感管道永久故障导致的国家腐败分析

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417024

Raghda El Shehaby, A. Steininger

{"title":"Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines","authors":"Raghda El Shehaby, A. Steininger","doi":"10.1109/DDECS52668.2021.9417024","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417024","url":null,"abstract":"Quasi delay-insensitive asynchronous circuits have the appealing property of stopping further operation in case of a permanent fault. This fail-stop behavior makes them attractive for on-line repair: after removal of the permanent fault, the circuit can, ideally, continue operating without the need for state recovery. However, it has been shown that in certain cases the state may get corrupted before the operation actually stops.In this paper we use the example of a weak-conditioned half-buffer template to investigate more closely which situations can lead to such state corruption. We explore implementation variants like double completion detection to mitigate that undesired effect. Based on extensive gate-level simulation experiments we quantify the probability for state corruption seen in the different circuits and identify the relevant dependences. As it turns out, the proposed extensions can reduce, but not completely eliminate, the risk of state corruption. At the same time detection of illegal code words promises to have great potential for countermeasures.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133806715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-μ m CMOS for reaching PDP saturation at 650 nm 全集成SPAD主动淬火/复位电路在高压0.35 μ m CMOS达到PDP饱和在650纳米

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417020

Alija Dervić, S. K. Poushi, H. Zimmermann

{"title":"Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-μ m CMOS for reaching PDP saturation at 650 nm","authors":"Alija Dervić, S. K. Poushi, H. Zimmermann","doi":"10.1109/DDECS52668.2021.9417020","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417020","url":null,"abstract":"This paper presents a fully-integrated optical sensor IC with SPAD, quenching/resetting circuit, and novel sensing stage based on a tunable-threshold inverter optimized for 0.35-μm high-voltage CMOS technology. The presented quencher features a controllable excess bias voltage and an adjustable total dead time. The excess bias voltage ranges from 10 V to a maximum of 22 V. The dead time ranges from 8 ns to 50 ns, which corresponds to a saturation count rate range from 20 Mcps to 125 Mcps. The quencher is optimized for the SPAD with a capacitance of 150 fF in the HV CMOS technology used. Using our recently published photon detection probability (PDP) model and fitting it to measured results up to a PDP of 68.8% at 9.9 V excess bias from our previous tapeout, a peak PDP of 90.1% (saturation PDP) at 650 nm for VEX=17.9 V is estimated and a PDP over 50% at 850 nm comes into reach for the same excess bias voltage. To the authors’ best knowledge, PDP saturation has never been reached before for an integrated SPAD.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"24 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124471503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Model-Based Framework to Assess the Reliability of Safety-Critical Applications 基于模型的安全关键应用可靠性评估框架

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417059

Lucas Matana Luza, A. Ruospo, A. Bosio, Ernesto Sánchez, L. Dilillo

{"title":"A Model-Based Framework to Assess the Reliability of Safety-Critical Applications","authors":"Lucas Matana Luza, A. Ruospo, A. Bosio, Ernesto Sánchez, L. Dilillo","doi":"10.1109/DDECS52668.2021.9417059","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417059","url":null,"abstract":"Solutions based on artificial intelligence and brain-inspired computations like Artificial Neural Networks (ANNs) are suited to deal with the growing computational complexity required by state-of-the-art electronic devices. Many applications that are being deployed using these computational models are considered safety-critical (e.g., self-driving cars), producing a pressing need to evaluate their reliability. Besides, state-of-theart ANNs require significant memory resources to store their parameters (e.g., weights, activation values), which goes outside the possibility of many resource-constrained embedded systems. In this light, Approximate Computing (AxC) has become a significant field of research to improve memory footprint, speed, and energy consumption in embedded and high-performance systems. The use of AxC can significantly reduce the cost of ANN implementations, but it may also reduce the inherent resiliency of this kind of application. On this scope, reliability assessments are carried out by performing fault injection test campaigns. The intent of the paper is to propose a framework that, relying on the results of radiation tests in Commercial-Off-The-Shelf (COTS) devices, is able to assess the reliability of a given application. To this end, a set of different radiation-induced errors in COTS memories is presented. Upon these, specific fault models are extracted to drive emulation-based fault injections.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130614010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An Open-source Library of Large Integer Polynomial Multipliers 一个大整数多项式乘法器的开源库

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-01-27 DOI: 10.1109/DDECS52668.2021.9417065

Malik Imran, Zain Ul Abideen, S. Pagliarini

引用次数: 6