2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献_第2页

Development of On-Chip Calibration for Hybrid Pixel Detectors 混合像素检测器片上标定技术的发展

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417021

P. Skrzypiec, R. Szczygiel

{"title":"Development of On-Chip Calibration for Hybrid Pixel Detectors","authors":"P. Skrzypiec, R. Szczygiel","doi":"10.1109/DDECS52668.2021.9417021","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417021","url":null,"abstract":"Semiconductor hybrid pixel detectors of X-ray radiation are recently commonly used in many fields, such as material science, medicine, and synchrotron measurements. One of the most common problems to be solved in the pixel detector design are offsets and gain spreads in the readout electronics, which come from very small sizes of the transistors used. The mentioned problem can be mitigated by implementing a “digital-assisted analog” design approach, where the offsets are corrected by trimming digital-to-analog converters (DACs), fed with proper digital data. To find the correct input value for each DAC, the execution of the calibrating procedure is necessary, which is usually run using assistive devices, such as PCs or FPGAs, and is a time-consuming task. This paper presents the concept of the pixel matrix detector on-chip calibration, that enables standalone improvement of the device accuracy. The proposed solution integrates the RISC-V-based microprocessor, Pixel Matrix Controller, and pixel matrix detector inside the single integrated circuit. The solution does not require data transfer out of the chip and is therefore significantly faster than off-chip methods.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131240026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient Neural Network Approximation via Bayesian Reasoning 基于贝叶斯推理的高效神经网络逼近

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417057

A. Savino, Marcello Traiola, S. Carlo, A. Bosio

引用次数: 5

AdequateDL: Approximating Deep Learning Accelerators

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417026

O. Sentieys, Silviu-Ioan Filip, David Briand, D. Novo, Etienne Dupuis, Ian O’Connor, A. Bosio

引用次数: 2

EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design 用于超低压体驱动IC设计的EKV MOS晶体管模型

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417051

L. Nagy, D. Arbet, M. Kovác, M. Potocný, Michal Sovcík, V. Stopjaková

引用次数: 1

Tutorial: Silicon Systems for Wireless LAN 教程:用于无线局域网的硅系统

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417056

Z. Stamenkovic, H. Aziza, Ernesto Sánchez, A. Bosio

引用次数: 0

Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment 包含评估的1T1R忆阻交叉棒实现的点积引擎行为模型

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417070

J. Wen, Markus Ulbricht, E. Pérez, Xin Fan, M. Krstic

{"title":"Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment","authors":"J. Wen, Markus Ulbricht, E. Pérez, Xin Fan, M. Krstic","doi":"10.1109/DDECS52668.2021.9417070","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417070","url":null,"abstract":"Memristor is an emerging electrical device that enables non-volatile storage and in-memory computing. The memristive crossbar with high memory density and low energy consumption has drawn much attention for the implementation of dot-product engines, which can be deployed in power-hungry applications with intensive multiply-accumulate operations. However, simulating the crossbar containing a group of memristors based on the device-level modeling is time consuming. In this paper, we propose a model to simulate the memristive crossbar with high flexibility and automation at the behavioral level to perform the vector-matrix multiplication. This system-level model captures the non-linearity of memristors aiming for fast and accurate simulation. With the significantly reduced simulation time, this model enables simulating the systems containing memristive crossbar with large scale like neural networks in a more practical way. Moreover, this model can be exploited to analyze the effects of variations, which provides a condition and contributes to revealing potential computational errors. A multilayer perceptron detecting breast cancer is simulated based on this model to assess the classification accuracy with the presence of variabilities.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126338660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Emerging Technologies: Challenges and Opportunities for Logic Synthesis 新兴技术:逻辑综合的挑战与机遇

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417062

A. Bosio, Mayeul Cantan, Cédric Marchand, Ian O’Connor, P. Fiser, A. Poittevin, Marcello Traiola

引用次数: 0

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition 基于自顶向下分解的多数电路逻辑再合成

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417058

Siang-Yun Lee, Heinz Riener, G. Micheli

引用次数: 2

A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis 用于直接数字合成的数控振荡器的可参数化凿子发生器

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417063

Vukan D. Damnjanovic, Marija L. Petrovic, V. Milovanovic

{"title":"A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis","authors":"Vukan D. Damnjanovic, Marija L. Petrovic, V. Milovanovic","doi":"10.1109/DDECS52668.2021.9417063","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417063","url":null,"abstract":"Numerically controlled oscillators (NCOs) as part of direct digital synthesizers (DDS) are important components in many digital communication subsystems, such as various digital modulation and demodulation schemes, up and down converters, radar, sonar and laser appliances, etc. The vast number of their beneficial characteristics is what makes NCOs so widely used. Taking this into account, a parameterizable generator of numerically controlled oscillators is implemented using Chisel hardware design language. The proposed generator provides a broad range of parameter configurations, such as input and output data types and widths, the number of different output samples, optional use of spur-reducing techniques or different input interfaces, just to name a few. Numerous generated instances have been tested in software simulations and mapped and tested onto a commercial FPGA platform. Obtained results proved that a generator of this kind can legitimately be compared with custom designed NCO modules, both in terms of performance and resource utilization.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"31 6-7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115651091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level 芯片级间歇电阻故障检测的嵌入式测试仪及其在板级的重用

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417064

Hassan Ebrahimi, H. Kerkhoff

{"title":"Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level","authors":"Hassan Ebrahimi, H. Kerkhoff","doi":"10.1109/DDECS52668.2021.9417064","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417064","url":null,"abstract":"No-fault-founds (NFFs) threaten the dependability of highly dependable systems in avionic and car industries. Moreover, they drastically increase the test and maintenance costs. One of the main causes of NFFs is intermittent resistive faults (IRFs). IRFs mostly occur due to unstable and marginal interconnections. This paper proposes a new periodic testing method to detect IRFs in interconnections at the chip and the board level. The proposed method is based on on-chip embedded test instruments (ETIs), which are scalable, fully digital, and With a low hardware cost. As a case study, a network-on-chip (NoC) infrastructure with a mesh topology has been utilised. The implementation of the testing method requires a small chip area and power consumption overheads being 3% and 2.5%, respectively. In this paper, first, IRF detection at the chip level has been investigated using simulation-based fault injections in selected interconnections of the NoC. Then, the effectiveness of the proposed method at the board level has been verified by hardware-based fault injections as well as thermal cycling experiments on actual solder joints. The experimental results demonstrated that the on-chip ETIs can be reused effectively to detect IRFs at the board level.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129257568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0