2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)最新文献

CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector CLD:一个准确的，具有成本效益和可扩展的运行时缓存泄漏检测器

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417071

Ameer Shalabi, Tara Ghasempouri, P. Ellervee, J. Raik

{"title":"CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector","authors":"Ameer Shalabi, Tara Ghasempouri, P. Ellervee, J. Raik","doi":"10.1109/DDECS52668.2021.9417071","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417071","url":null,"abstract":"Cache logical side channel attacks pose a significant threat to the security of modern computer systems. This is a result of exploitation of cache information leakages arising from cache contention. Detection of such leakages can be inferred from cache behavior and processes’ access patterns during run time. To achieve this, a detection template that uses available information on cache outputs and process accesses at run-time is required. In this work, such template is proposed and implemented as a hardware monitor called Cache Leakage Detector (CLD). CLD is a high-accuracy, cost-effective and scalable run-time cache information leakage detector. CLD uses cache signals and process IDs to detect exploitable cache access patterns. It does so by identifying potential information leakage patterns. Accuracy of CLD is evaluated by using several benchmarks and injecting attacks into a 128-bit key AES algorithm. The experiments demonstrate that CLD has far higher detection accuracy (0.7964 vs 0.3195) and lower percentage of false positive detections (1.2% vs 30.6%) compared to a state-of-the-art hardware detector. Moreover, CLD introduces a very low area overhead of 0.002% to the total area of the cache. Experimental result section reports the above claims in detail.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124848068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Prevention and Detection Methods of Systematic Failures in the Implementation of SoC Safety Mechanisms not Covered by Regular Functional Tests 常规功能测试未涵盖的SoC安全机制实施中系统性故障的预防和检测方法

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417073

D. Dutey, Stephane Martin, Anne Merlande, Om Ranjan

引用次数: 1

A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores 针对流水线微处理器内核的rt级硬件木马的基准测试套件

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417061

A. Damljanovic, A. Ruospo, Ernesto Sánchez, Giovanni Squillero

{"title":"A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores","authors":"A. Damljanovic, A. Ruospo, Ernesto Sánchez, Giovanni Squillero","doi":"10.1109/DDECS52668.2021.9417061","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417061","url":null,"abstract":"Recent trends in integrated circuits industry include decentralization of the production flow by involving different integration teams, third-party IP vendors and other untrusted entities. As a result, this is opening up a door to new types of attacks that may lead to devastating consequences, such as denial of service or data leakage. Therefore, the problem of ensuring hardware security has gained much attention in the last years, especially early in the design cycle, when an attacker may insert malicious circuitry at register transfer (RT) or gate level. Due to the increased complexity of modern devices, the research community is spending a lot of effort in developing more sophisticated detection methodologies and smarter attacks. However, the main problem is that they are validated on the existing benchmarks that do not reflect the real complexity. Trying to fill this gap, this paper proposes a set of RT-Level Hardware Trojan benchmarks injected in a RISC-based pipelined microprocessor core. To prove the viability, the impacts on area, power and frequency are presented and discussed. For any proposed Hardware Trojan, the functional description, the implementation details and the effects once activated are provided.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129694275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Approximate Multipliers for Optimal Utilization of FPGA Resources 近似乘法器对FPGA资源的最佳利用

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417027

Christoph Niemann, Michael Rethfeldt, D. Timmermann

{"title":"Approximate Multipliers for Optimal Utilization of FPGA Resources","authors":"Christoph Niemann, Michael Rethfeldt, D. Timmermann","doi":"10.1109/DDECS52668.2021.9417027","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417027","url":null,"abstract":"Approximate or inexact arithmetic is a promising approach towards lower power consumption for applications that can tolerate a certain amount of imprecision. As human perception is limited in its precision, this applies to image and audio processing. Beyond, other applications like neuronal networks or AI processing can benefit from such arithmetic as well, as they are inherently tolerant to a certain amount of inaccuracy. One of the most critical components of arithmetic circuits regarding power, delay, and area are multipliers. Various sophisticated approaches towards approximate multipliers are already published for ASICs. However, such ASIC approaches are under-performing in conjunction with the specific Lookup-Table (LUT)-based design of FPGAs. As FPGAs gain in importance for applications like signal processing, there is a substantial lack of approximate design methodology for FPGAs. We propose an approach towards approximate signal processing that is specifically tailored towards the LUT-based hardware of FPGAs. It allows for significant performance improvements while lowering the energy demands. While introducing an insignificant average relative error of just 0.14%, we achieve a 45.9% area reduction in terms of LUTs while decreasing the delay by 30.6% compared to the Xilinx Vivado multiplier IP core. Our proposed design is open source and available at https://github.com/niemann-c/approx-mult-for-fpga.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"16 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132498426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

HEIST: A Hardware Signal Fault Injection Methodology Enabling Feasible Software Robustness Testing HEIST:一种硬件信号故障注入方法，支持可行的软件稳健性测试

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417053

Martin Skriver, A. S. Sørensen, U. Schultz

{"title":"HEIST: A Hardware Signal Fault Injection Methodology Enabling Feasible Software Robustness Testing","authors":"Martin Skriver, A. S. Sørensen, U. Schultz","doi":"10.1109/DDECS52668.2021.9417053","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417053","url":null,"abstract":"In this paper we investigate the use of FPGAs to inject faults into data streams as a supplement to the international EMC-test standards. We aim to test the robustness and reliability of software based measures against the effects of electromagnetic interference. The proposed methodology, HEIST, uses high-speed acquisition of faulty data and high-speed fault injection. HEIST requires less insight into electromagnetism and electronics compared to other iterative EMC qualification processes. This is particularly relevant in designs where a strategy of 100% hardware-based noise avoidance is not feasible, and software based noise handling has been implemented as a supplement. Such situations are typical in mobile light-weight systems such as drones, where shielding and hardware filters add undesirable weight. The methodology is verified by comparing data from a serial communication link that has been exposed to burst noise based on the IEC 61000-4-4 test standard with data from the same setup, but replacing the burst generator with the HEIST approach. The result shows an excellent correlation indicating that HEIST can replace the burst generator for a software EMC test in an ongoing software development process.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130984861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array 游标时间-数字转换器像素阵列的测试验证环境与方法

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417054

L. Kadlubowski, P. Kmon

引用次数: 3

Q-Learning-based Routing Algorithm for 3D Network-on-Chips 基于q -学习的三维片上网络路由算法

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417050

Nurettin Bölücü, S. Tosun

引用次数: 0

Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis 用于加密网络流量分析的决策树算法的高效加速

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417068

R. Vrána, J. Korenek

{"title":"Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis","authors":"R. Vrána, J. Korenek","doi":"10.1109/DDECS52668.2021.9417068","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417068","url":null,"abstract":"Network traffic analysis and deep packet inspection are time-consuming tasks, which current processors can not handle at 100 Gbps speed. Therefore security systems need fast packet processing with hardware acceleration. With the growing of encrypted network traffic, it is necessary to extend Intrusion Detection Systems (IDSes) and other security tools by new detection methods. Security tools started to use classifiers trained by machine learning techniques based on decision trees. Random Forest, Compact Random Forest and AdaBoost provide excellent result in network traffic analysis. Unfortunately, hardware architectures for these machine learning techniques need high utilisation of on-chip memory and logic resources. Therefore we propose several optimisations of highly pipelined architecture for acceleration of machine learning techniques based on decision trees. The optimisations use the various encoding of a feature vector to reduce hardware resources. Due to the proposed optimisations, it was possible to reduce LUTs by 70.5 % for HTTP brute force attack detection and BRAMs by 50 % for application protocol identification. Both with only negligible impact on classifiers’ accuracy. Moreover, proposed optimisations reduce wires and multiplexors in the processing pipeline, positively affecting the proposed architecture’s maximal achievable frequency.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114818678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults 用模型检查器对数字电路的延迟故障进行分析和测试

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417069

Josef Strnadel

{"title":"Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults","authors":"Josef Strnadel","doi":"10.1109/DDECS52668.2021.9417069","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417069","url":null,"abstract":"Narrow timing margins in modern digital circuits result in delay defects that are difficult to detect. The probability that such a defect occurs increases with factors such as shrinking feature sizes, increasing process variations, operating frequencies, and aging/stress of the circuits. Traditionally, timing is considered in connection with the logic design, physical design and layout, and delay testing phases of the circuit development process and builds on principles of delay characterization, fault models and timing analysis. This paper presents a model checking approach aiming to facilitate the solutions of problems with regard to analyzing consequences and testing of delay faults. Our approach expects that a circuit is modeled as a network of stochastic hybrid timed automata capable to describe the circuit both in the logical and temporal domains, including facts such as uncertainty and variations. In our approach, we gather attributes and formalize expected properties of a circuit and transform the circuit into our model. Then, we use a statistical model checker to check the properties and to produce a counter-example for each property being violated. Further, we transform the counter-examples into test cases and finally, into a delay test able to check whether the timing requirements are met.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117237954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration 通过片上数字校准提高全差分放大器的可靠性

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2021-04-07 DOI: 10.1109/DDECS52668.2021.9417022

D. Maljar, Michal Sovcík, D. Arbet, V. Stopjaková

{"title":"Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration","authors":"D. Maljar, Michal Sovcík, D. Arbet, V. Stopjaková","doi":"10.1109/DDECS52668.2021.9417022","DOIUrl":"https://doi.org/10.1109/DDECS52668.2021.9417022","url":null,"abstract":"This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20° C to 85° C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 μV to 167 μV). The concept proposed in this work utilizes advanced high precision calibration algorithm.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117246008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0