Ameer Shalabi, Tara Ghasempouri, P. Ellervee, J. Raik
{"title":"CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector","authors":"Ameer Shalabi, Tara Ghasempouri, P. Ellervee, J. Raik","doi":"10.1109/DDECS52668.2021.9417071","DOIUrl":null,"url":null,"abstract":"Cache logical side channel attacks pose a significant threat to the security of modern computer systems. This is a result of exploitation of cache information leakages arising from cache contention. Detection of such leakages can be inferred from cache behavior and processes’ access patterns during run time. To achieve this, a detection template that uses available information on cache outputs and process accesses at run-time is required. In this work, such template is proposed and implemented as a hardware monitor called Cache Leakage Detector (CLD). CLD is a high-accuracy, cost-effective and scalable run-time cache information leakage detector. CLD uses cache signals and process IDs to detect exploitable cache access patterns. It does so by identifying potential information leakage patterns. Accuracy of CLD is evaluated by using several benchmarks and injecting attacks into a 128-bit key AES algorithm. The experiments demonstrate that CLD has far higher detection accuracy (0.7964 vs 0.3195) and lower percentage of false positive detections (1.2% vs 30.6%) compared to a state-of-the-art hardware detector. Moreover, CLD introduces a very low area overhead of 0.002% to the total area of the cache. Experimental result section reports the above claims in detail.","PeriodicalId":415808,"journal":{"name":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS52668.2021.9417071","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Cache logical side channel attacks pose a significant threat to the security of modern computer systems. This is a result of exploitation of cache information leakages arising from cache contention. Detection of such leakages can be inferred from cache behavior and processes’ access patterns during run time. To achieve this, a detection template that uses available information on cache outputs and process accesses at run-time is required. In this work, such template is proposed and implemented as a hardware monitor called Cache Leakage Detector (CLD). CLD is a high-accuracy, cost-effective and scalable run-time cache information leakage detector. CLD uses cache signals and process IDs to detect exploitable cache access patterns. It does so by identifying potential information leakage patterns. Accuracy of CLD is evaluated by using several benchmarks and injecting attacks into a 128-bit key AES algorithm. The experiments demonstrate that CLD has far higher detection accuracy (0.7964 vs 0.3195) and lower percentage of false positive detections (1.2% vs 30.6%) compared to a state-of-the-art hardware detector. Moreover, CLD introduces a very low area overhead of 0.002% to the total area of the cache. Experimental result section reports the above claims in detail.
高速缓存逻辑侧信道攻击对现代计算机系统的安全构成重大威胁。这是利用缓存争用引起的缓存信息泄漏的结果。这种泄漏的检测可以从缓存行为和进程在运行时的访问模式中推断出来。为此,需要一个检测模板,该模板在运行时使用有关缓存输出和进程访问的可用信息。在这项工作中,该模板被提出并实现为一个称为缓存泄漏检测器(CLD)的硬件监视器。CLD是一种高精度、高性价比、可扩展的运行时缓存信息泄漏检测器。CLD使用缓存信号和进程id来检测可利用的缓存访问模式。它通过识别潜在的信息泄漏模式来实现这一点。通过使用多个基准测试和向128位密钥AES算法注入攻击来评估CLD的准确性。实验表明,与最先进的硬件检测器相比,CLD具有更高的检测精度(0.7964 vs 0.3195)和更低的假阳性检测百分比(1.2% vs 30.6%)。此外,CLD带来的区域开销非常低,仅占缓存总面积的0.002%。实验结果部分详细报道了上述权利要求。