Development of On-Chip Calibration for Hybrid Pixel Detectors

Abstract

Semiconductor hybrid pixel detectors of X-ray radiation are recently commonly used in many fields, such as material science, medicine, and synchrotron measurements. One of the most common problems to be solved in the pixel detector design are offsets and gain spreads in the readout electronics, which come from very small sizes of the transistors used. The mentioned problem can be mitigated by implementing a “digital-assisted analog” design approach, where the offsets are corrected by trimming digital-to-analog converters (DACs), fed with proper digital data. To find the correct input value for each DAC, the execution of the calibrating procedure is necessary, which is usually run using assistive devices, such as PCs or FPGAs, and is a time-consuming task. This paper presents the concept of the pixel matrix detector on-chip calibration, that enables standalone improvement of the device accuracy. The proposed solution integrates the RISC-V-based microprocessor, Pixel Matrix Controller, and pixel matrix detector inside the single integrated circuit. The solution does not require data transfer out of the chip and is therefore significantly faster than off-chip methods.