2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献_第6页

Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology 12纳米FinFET技术的蓝牙低能量发射器的开源可完全合成ADPLL

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863190

Kyumin Kwon, Omar Abdelatty, D. Wentzloff

{"title":"Open-Source Fully-Synthesizable ADPLL for a Bluetooth Low-Energy Transmitter in 12nm FinFET Technology","authors":"Kyumin Kwon, Omar Abdelatty, D. Wentzloff","doi":"10.1109/RFIC54546.2022.9863190","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863190","url":null,"abstract":"In this work, we present an open-source fully-synthesizable fractional-N ADPLL designed for a Bluetooth Low-Energy (BLE) transmitter (TX). A highly automated design flow is used to lower the barrier for new developers and to reduce porting cost. In the PLL, a novel two-step TDC (TSTDC) is proposed, which is amenable to P&R, and uses an embedded TDC (EMBTDC) and vernier delay-line TDC (DLTDC) as coarse and fine TDCs, respectively. This combination reduces the required DLTDC input time range by 5x and is used to measure and compensate the P&R induced non-linearity of the EMBTDC. The PLL is fabricated in 12-nm FinFET and demonstrated in a BLE-TX. BLE transmissions satisfy the standard requirements thanks to the reduced fractional spurs by abovementioned techniques. In a standalone PLL mode, the TSTDC reduced fractional spurs by 6.8 dB compared to an EMBTDC alone, and the proposed LUT-based calibration further reduced spurs by 7.5 dB in near-integer operation. The PLL supports frequency range of 1.8-2.7GHz and consumes 3.91mW at 2.4006 GHz, with a 40MHz reference, occupying area of 0.063mm2.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123638262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fully Integrated Ultra-Wideband Differential Circulator Based on Sequentially Switched Delay Line in 28-nm FDSOI CMOS 基于顺序开关延迟线的28纳米FDSOI CMOS全集成超宽带差分环行器

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863099

J. Hwang, Byung-Wook Min

引用次数: 1

A 28 GHz/39 GHz Dual-Band Four-Element MIMO RX with Beamspace Multiplexing at IF in 65-nm CMOS 基于65纳米CMOS的28 GHz/39 GHz双频四元MIMO RX中频波束空间复用技术

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863191

Robin Garg, Paul Dania, Gaurav Sharma, Armagan Dascurcu, Soumya Gupta, H. Krishnaswamy, A. Natarajan

引用次数: 0

An E-Band Phase Modulated Pulse Radar SoC with An Analog Correlator 带模拟相关器的e波段相位调制脉冲雷达SoC

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863185

Wen Zhou, Y. Tousi

引用次数: 0

A 5.1 dBm 127–162 GHz Frequency Sextupler with Broadband Compensated Transformer-Based Baluns in 22nm FD-SOI CMOS 基于22nm FD-SOI CMOS的带宽带补偿变压器平衡器的5.1 dBm 127-162 GHz频率六倍器

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863124

Shuyang Li, Wen-hua Chen, Xingcun Li, Yunfan Wang

引用次数: 4

DC to 12+GHz, +30dBm OIP3, 7.2dB Noise Figure Active Balun in 130nm BiCMOS for RF Sampling Multi-Gbps Data Converters DC至12+GHz， +30dBm OIP3, 7.2dB噪声图有源Balun在130nm BiCMOS射频采样多gbps数据转换器

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863207

S. Akhtar, G. Schuppener, T. Dinc, B. Haroun, S. Sankaran

引用次数: 0

An Integrated Quantum Spin Control System in 180nm CMOS 180nm CMOS集成量子自旋控制系统

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863137

Kaisarbek Omirzakhov, M. H. Idjadi, Tzu-Yung Huang, S. Breitweiser, David A. Hopper, L. Bassett, F. Aflatouni

引用次数: 1

A 2Gb/s 9.9pJ/b Sub-10GHz Wireless Transceiver for Reconfigurable FDD Wireless Networks and Short-Range Multicast Applications 用于可重构FDD无线网络和短距离组播应用的2Gb/s 9.9pJ/b Sub-10GHz无线收发器

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863181

Renzhi Liu, Beevi K. T. Asma, R. Dorrance, T. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, B. Carlton

引用次数: 2

A 8–30 GHz Passive Harmonic Rejection Mixer with 8 GHz Instantaneous IF Bandwidth in 45RFSOI 45RFSOI中8 GHz瞬时中频带宽的8 - 30 GHz无源谐波抑制混频器

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863130

Amr Ahmed, Gabriel M. Rebeiz

引用次数: 1

A 59-fs-rms 35-GHz PLL with FoM of −241-dB in $0.18-mu mathrm{m}$ BiCMOS/SiGe Technology 一个59-fs-rms 35-GHz锁相环，FoM为- 241-dB，采用$0.18-mu mathrm{m}$ BiCMOS/SiGe技术

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2022-06-19 DOI: 10.1109/RFIC54546.2022.9863116

Rajath Bindiganavile, Asif Wahid, Jacob Atkinson, A. Tajalli

{"title":"A 59-fs-rms 35-GHz PLL with FoM of −241-dB in $0.18-mu mathrm{m}$ BiCMOS/SiGe Technology","authors":"Rajath Bindiganavile, Asif Wahid, Jacob Atkinson, A. Tajalli","doi":"10.1109/RFIC54546.2022.9863116","DOIUrl":"https://doi.org/10.1109/RFIC54546.2022.9863116","url":null,"abstract":"A wideband and ultra low-noise Phase-Locked Loop (PLL) circuit is designed and implemented in a $0.18 mu mathrm{m}$ BiCMOS/SiGe technology to operate at a nominal frequency of 35.68 GHz. Incorporating a multi-phase phase frequency detector along with a high frequency reference signal, the bandwidth of the PLL was maximized to reduce the phase noise and jitter contribution of the forward path loop components within the frequency band of interest. A multi-phase phase comparator also relaxes the constraints imposed by the sampling nature of the PLL, allowing for a more convenient performance optimization with reduced jitter peaking and more optimal loop characteristics. The PLL was measured to have a Phase Noise of −113.3 dBc/Hz at an offset frequency of 1 MHz, and a total integrated jitter of 59 fs-rms integrated from 1 kHz to 100 MHz, consuming 194.6 mW with a jitter-power FoM −241.6 dB. The power dissipation of the proposed PLL is lower than implementations in similar technology nodes, while obviously higher than designs made in advanced CMOS/FinFET technologies. The PLL has been designed in BiCMOS/SiGe $0.18 mu mathrm{m}$, aiming to be integrated together with power amplifiers in a 3D structure targeted for the next generation 5G systems.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128286696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0