2017 IEEE International Electron Devices Meeting (IEDM)最新文献_第9页

Nanofluidics for cell and drug delivery 用于细胞和药物输送的纳米流体

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268529

N. Di Trani, A. Grattoni, M. Ferrari

引用次数: 1

Progress and future challenges of SiC power devices and process technology SiC功率器件和工艺技术的进展和未来挑战

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268360

T. Kimoto, H. Niwa, N. Kaji, T. Kobayashi, Y. Zhao, S. Mori, M. Aketa

引用次数: 15

Perspective of negative capacitance FinFETs investigated by transient TCAD simulation 瞬态TCAD仿真研究负电容finfet的前景

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268394

H. Ota, K. Fukuda, T. Ikegami, J. Hattori, H. Asai, S. Migita, A. Toriumi

引用次数: 20

Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs 单片3D集成MX2 fet与Si finfet的基准测试

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268336

T. Agarwal, Á. Szabó, M. Bardon, B. Sorée, I. Radu, P. Raghavan, M. Luisier, W. Dehaene, M. Heyns

引用次数: 9

Rapid antibiotic susceptibility testing system: Life saving bioMEMS devices 快速抗生素药敏检测系统:拯救生命的bioMEMS设备

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268364

H. Y. Jeong, E.-G. Kim, S. Han, G. Y. Lee, B. Jin, T. Lim, H. C. Kim, T. S. Kim, D. Y. Kim, S. Kwon

引用次数: 0

Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology 像素/DRAM/逻辑3层堆叠CMOS图像传感器技术

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268317

H. Tsugawa, H. Takahashi, R. Nakamura, T. Umebayashi, T. Ogita, H. Okano, K. Iwase, H. Kawashima, T. Yamasaki, D. Yoneyama, J. Hashizume, T. Nakajima, K. Murata, Y. Kanaishi, K. Ikeda, K. Tatani, T. Nagano, H. Nakayama, T. Haruta, T. Nomoto

引用次数: 28

A single magnetic-tunnel-junction stochastic computing unit 单磁隧道结随机计算单元

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268504

Yang Lv, Jianping Wang

引用次数: 28

A back-illuminated 3D-stacked single-photon avalanche diode in 45nm CMOS technology 45纳米CMOS技术的背照3d堆叠单光子雪崩二极管

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268405

Myung-Jae Lee, A. Ximenes, Preethi Padmanabhan, Tzu-Jui Wang, Kuo-Chin Huang, Y. Yamashita, D. Yaung, E. Charbon

引用次数: 17

Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays 随机稀疏自适应对不精确的多级随机随机存储器阵列进行精确推断

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268339

Abinash Mohanty, Xiaocong Du, Pai-Yu Chen, Jae-sun Seo, Shimeng Yu, Yu Cao

{"title":"Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays","authors":"Abinash Mohanty, Xiaocong Du, Pai-Yu Chen, Jae-sun Seo, Shimeng Yu, Yu Cao","doi":"10.1109/IEDM.2017.8268339","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268339","url":null,"abstract":"An array of multi-level resistive memory devices (RRAMs) can speed up the computation of deep learning algorithms. However, when a pre-trained model is programmed to a real RRAM array for inference, its accuracy degrades due to many non-idealities, such as variations, quantization error, and stuck-at faults. A conventional solution involves multiple read-verify-write (R-V-W) for each RRAM cell, costing a long time because of the slow Write speed and cell-by-cell compensation. In this work, we propose a fundamentally new approach to overcome this issue: random sparse adaptation (RSA) after the model is transferred to the RRAM array. By randomly selecting a small portion of model parameters and mapping them to on-chip memory for further training, we demonstrate an efficient and fast method to recover the accuracy: in CNNs for MNIST and CIFAR-10, ∼5% of model parameters is sufficient for RSA even under excessive RRAM variations. As the back-propagation in training is only applied to RSA cells and there is no need of any Write operation on RRAM, the proposed RSA achieves 10–100X acceleration compared to R-V-W. Therefore, this hybrid solution with a large, inaccurate RRAM array and a small, accurate on-chip memory array promises both area efficiency and inference accuracy.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126034625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects 一种10nm高性能低功耗CMOS技术，具有第三代FinFET晶体管，自对准四面图，主动栅极接触和钴本地互连

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI: 10.1109/IEDM.2017.8268472

C. Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, V. Bhagwat, J. Birdsall, N. Bisnik, M. Buehler, V. Chikarmane, G. Ding, Q. Fu, H. Gomez, W. Han, D. Hanken, M. Haran, M. Hattendorf, R. Heussner, H. Hiramatsu, B. Ho, S. Jaloviar, I. Jin, S. Joshi, S. Kirby, S. Kosaraju, H. Kothari, G. Leatherman, K. Lee, J. Leib, A. Madhavan, K. Marla, H. Meyer, T. Mule, C. Parker, S. Parthasarathy, C. Pelto, L. Pipes, I. Post, M. Prince, A. Rahman, S. Rajamani, A. Saha, J. D. Santos, M. Sharma, V. Sharma, J. Shin, P. Sinha, P. Smith, M. Sprinkle, A. Amour, C. Staus, R. Suri, D. Towner, A. Tripathi, A. Tura, C. Ward, A. Yeoh

{"title":"A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects","authors":"C. Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, V. Bhagwat, J. Birdsall, N. Bisnik, M. Buehler, V. Chikarmane, G. Ding, Q. Fu, H. Gomez, W. Han, D. Hanken, M. Haran, M. Hattendorf, R. Heussner, H. Hiramatsu, B. Ho, S. Jaloviar, I. Jin, S. Joshi, S. Kirby, S. Kosaraju, H. Kothari, G. Leatherman, K. Lee, J. Leib, A. Madhavan, K. Marla, H. Meyer, T. Mule, C. Parker, S. Parthasarathy, C. Pelto, L. Pipes, I. Post, M. Prince, A. Rahman, S. Rajamani, A. Saha, J. D. Santos, M. Sharma, V. Sharma, J. Shin, P. Sinha, P. Smith, M. Sprinkle, A. Amour, C. Staus, R. Suri, D. Towner, A. Tripathi, A. Tura, C. Ward, A. Yeoh","doi":"10.1109/IEDM.2017.8268472","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268472","url":null,"abstract":"A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-aligned contact over active gate process and elimination of the dummy gate at cell boundaries are introduced. The transistors feature rectangular fins with 7nm fin width and 46nm fin height, 5th generation high-k metal gate, and 7th-generation strained silicon. Four or six workfunction metal stacks are used to enable undoped fins for low Vt, standard Vt and optional high Vt devices. Interconnects feature 12 metal layers with ultra-low-k dielectrics throughout the interconnect stack. The highest drive currents with the highest cell densities are reported for a 10nm technology.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121679631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 267